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| 型號： | MC9328MX21SCVK |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 10/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU I.MX21 266MHZ 289-MAPBGA |
| 標準包裝： | 152 |
| 系列： | i.MX21 |
| 核心處理器： | ARM9 |
| 芯體尺寸： | 32-位 |
| 速度： | 266MHz |
| 連通性： | 1 線，EBI/EMI，I²C，IrDA，MMC，智能卡，SPI，SSI，UART/USART，USB OTG |
| 外圍設備： | DMA，I²S，LCD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 192 |
| 程序存儲器類型： | ROMless |
| 電壓 - 電源 (Vcc/Vdd)： | 1.45 V ~ 3.3 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 289-LFBGA |
| 包裝： | 托盤 |
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MC9328MX21S Technical Data, Rev. 1.3
18
Freescale Semiconductor
Specifications
3.7
External DMA Request and Grant
The External DMA request is an active low signal to be used by devices external to i.MX21 processor to
request the DMAC for data transfer.
After assertion of External DMA request the DMA burst will start when the channel on which the External
request is the source (as per the RSSR settings) becomes the current highest priority channel. The external
device using the External DMA request should keep its request asserted until it is serviced by the DMAC.
One External DMA request will initiate one DMA burst.
The output External Grant signal from the DMAC is an active-low signal.When the following conditions
are true, the External DMA Grant signal is asserted with the initiation of the DMA burst.
The DMA channel for which the DMA burst is ongoing has request source as external DMA Request
(as per source select register setting).
REN and CEN bit of this channel are set.
External DMA Request is asserted.
After the grant is asserted, the External DMA request will not be sampled until completion of the DMA
burst. As the external request is synchronized, the request synchronization will not be done during this
period. The priority of the external request becomes low for the next consecutive burst, if another DMA
request signal is asserted.
Worst case—that is, the smallest burst (1 byte read/write) timing diagrams are shown in Figure 4 and
Figure 5. Minimum and maximum timings for the External request and External grant signals are present
in Table 13.
Figure 4 shows the minimum time for which the External Grant signal remains asserted when an External
DMA request is de-asserted immediately after sensing grant signal active.
Table 12. Reset Module Timing Parameters
Ref
No.
Parameter
1.8 V
± 0.10 V 3.0 V ± 0.30 V
Unit
Min
Max
Min
Max
1
Width of input POWER_ON_RESET
800
–
800
–
ms
2
Width of internal POWER_ON_RESET
(CLK32 at 32 kHz)
300
ms
3
7k to 32k-cycle stretcher for SDRAM reset
7
Cycles of CLK32
4
14k to 32k-cycle stretcher for internal system reset HRESERT
and output reset at pin RESET_OUT
14
Cycles of CLK32
5
Width of external hard-reset RESET_IN
4
–
4
–
Cycles of CLK32
6
4k to 32k-cycle qualifier
4
Cycles of CLK32
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX21
Product
Family
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC9328MX21SCVKR2 | 功能描述:處理器 - 專門應用 DB I.MX21S RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21SCVM | 功能描述:處理器 - 專門應用 DB I.MX21 17X17 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21SCVMR2 | 功能描述:處理器 - 專門應用 DB I.MX21 17X17 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21SVK | 功能描述:處理器 - 專門應用 DB I.MX21S RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21SVKR2 | 功能描述:處理器 - 專門應用 DB I.MX21S RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
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