參數(shù)資料
型號： MC9328MX21DVMR2
廠商： Freescale Semiconductor
文件頁數(shù)： 10/100頁
文件大小： 0K
描述： IC MCU I.MX21 266MHZ 289-MAPBGA
標(biāo)準(zhǔn)包裝： 1,000
系列： i.MX21
核心處理器： ARM9
芯體尺寸： 32-位
速度： 266MHz
連通性： 1 線，EBI/EMI，I²C，IrDA，MMC，智能卡，SPI，SSI，UART/USART，USB OTG
外圍設(shè)備： DMA，I²S，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 192
程序存儲器類型： ROMless
電壓 - 電源 (Vcc/Vdd)： 1.45 V ~ 3.3 V
振蕩器型： 外部
工作溫度： -30°C ~ 70°C
封裝/外殼： 289-LFBGA
包裝： 帶卷 (TR)
Specifications
MC9328MX21 Technical Data, Rev. 3.4
Freescale Semiconductor
17
All timing is measured at 30 pF loading with the exception of fast I/O signals as discussed below. Refer
to the reference manual’s System Control Chapter for details on drive strength settings.
Table 8 provides the maximum loading guidelines that can be tolerated on a memory I/O signal (also
known as Fast I/O) to achieve 133 MHz operation. These critical signals include the SDRAM Clock
(SDCLK), Data Bus signals (D[31:0]), lower order address signals such as A0-A10, MA10, MA11, and
other signals required to meet 133 MHz timing.
The values shown in Table 8 apply over the recommended operating temperature range. Care must be
taken to minimize parasitic capacitance of associated printed circuit board traces.
3.5
DPLL Timing Specifications
Parameters of the DPLL are given in Table 11. In this table, Tref is a reference clock period after the
predivider and Tdck is the output double clock period.
Table 8. Loading Guidelines for Fast IO Signals to Achieve 133 MHz Operation
Drive Strength Setting (DSCR2–DSCR12)
Maximum I/O Loading at 1.8 V
Maximum I/O Loading at 3.0 V
000: 3.5 mA
9 pF
12 pF
001: 4.5 mA
12 pF
16 pF
011: 5.5 mA
15 pF
21 pF
111: 6.5 mA
19 pF
26 pF
Table 9. 32k/26M Oscillator Signal Timing
Parameter
Minimum
RMS
Maximum
Unit
EXTAL32k input jitter (peak to peak) for both System PLL and MCUPLL
–
5
20
ns
EXTAL32k input jitter (peak to peak) for MCUPLL only
–
5
100
ns
EXTAL32k startup time
800
–
ms
Table 10. CLKO Rise/Fall Time (at 30pF Loaded)
Best Case
Typical
Worst Case
Units
Rise Time
0.80
1.00
1.40
ns
Fall Time
0.74
1.08
1.67
ns
Table 11. DPLL Specifications
Parameter
Test Conditions
Minimum
Typical
Maximum
Unit
Reference clock frequency range
Vcc = 1.5V
16
–
320
MHz
Pre-divider output clock frequency
range
Vcc = 1.5V
16
–
32
MHz
Double clock frequency range
Vcc = 1.5V
220
–
560
MHz
Pre-divider factor (PD)
–
1
–
16
–
Total multiplication factor (MF)
Includes both integer and fractional parts
5
–
15
–
相關(guān)PDF資料
PDF描述
S912XDT256F1MAL IC MCU FLASH 112-LQFP
MC9328MX21DVM IC MCU I.MX21 266MHZ 289-MAPBGA
MC9328MX21VM IC MCU I.MX21 266MHZ 289-MAPBGA
MCIMX357DJQ5CR2 MULTIMEDIA PROCESSOR 400-MAPBGA
S912XDQ256F1MAG IC MCU 16BIT 256KB FLASH 144LQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC9328MX21S 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:i.MX family of microprocessors 266 MHz
MC9328MX21S_08 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:i.MX family of microprocessors 266 MHz
MC9328MX21SCVK 功能描述:處理器 - 專門應(yīng)用 DB I.MX21S RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MC9328MX21SCVKR2 功能描述:處理器 - 專門應(yīng)用 DB I.MX21S RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MC9328MX21SCVM 功能描述:處理器 - 專門應(yīng)用 DB I.MX21 17X17 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*