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| 型號： | MC9328MX21DVK |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, MICROPROCESSOR, PBGA289 |
| 封裝： | 14 X 14 MM, 1.41 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, PLASTIC, MAPBGA-289 |
| 文件頁數(shù)： | 20/100頁 |
| 文件大?。?/td> | 1979K |
| 代理商： | MC9328MX21DVK |
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MC9328MX21 Technical Data, Rev. 3.4
26
Freescale Semiconductor
Specifications
Figure 10. Memory Interface Slave Mode, External Bus Master Read/Write to BMI Timing
(MMD_MODE_SEL=0, MASTER_MODE_SEL=0)
Note:
All the timings are assumed that the hclk is running at 133 MHz.
3.8.3
Connecting BMI to External Bus Slave Devices
In this mode the BMI_WRITE, BMI_READ and BMI_CLK/CS are output signals driving by the BMI
module. The output signal BMI_READ_REQ is still driving active-in on a write cycle, but it can be
ignored in this case. Instead, it is used to trigger internal logic to generate the read or write signals. Data
write cycles are continuously generated when TxFIFO is not emptied.
To issue a read cycle, the user can write a value of 1 to the READ bit of control register. This bit is cleared
automatically when the read operation is completed. A read cycle reads COUNT+1 data from the external
bus slave. The user can write a 1 to the READ bit while there is still data in the TxFIFO, but the read cycle
will not start until all data in the TxFIFO is emptied. If the read cycle begins, the write operation also
cannot begin until this read cycle complete.
In this master mode operation, Int_Clk is derived from HCLK through an integer divider DIV of BMI
control register and it is used to control the read/write cycle timing by generate WRITE and CLK/CS
signals.
Table 18. External Bus Master Read/Write to BMI Timing Table
Item
Symbol
Minimum
Typical
Maximum
Unit
Write setup time
Ts
11
–
ns
Write hold time
Th
0
–
ns
Receive data hold time
Trdh
3
–
ns
Transfer data setup time
Ttds
6
–
14
ns
Transfer data hold time
Ttdh
6
–
14
ns
Read_req hold time
Trh
6
–
24
ns
BMI_CLK/CS
BMI_READ_REQ
BMI_WRITE
BMI_D[15:0]
RxD
TxD
Last TxD
Read
BMI
Write
BMI
Read
BMI
Trdh
Trh
Th
Ts
Ttds
Ttdh
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC9328MX21DVK | 制造商:Freescale Semiconductor 功能描述:Microprocessor |
| MC9328MX21DVKR2 | 功能描述:處理器 - 專門應(yīng)用 DB I.MX21 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21DVM | 功能描述:處理器 - 專門應(yīng)用 DB I.MX21 17X17 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21DVMR2 | 功能描述:處理器 - 專門應(yīng)用 DB I.MX21 17X17 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21S | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:i.MX family of microprocessors 266 MHz |
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