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參數(shù)資料
| 型號： | MC9328MX21CVH |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 266 MHz, MICROPROCESSOR, PBGA289 |
| 封裝： | 17 X 17 MM, 1.45 MM HEIGHT, 0.80 MM PITCH, MAPBGA-289 |
| 文件頁數(shù)： | 21/106頁 |
| 文件大?。?/td> | 1932K |
| 代理商： | MC9328MX21CVH |
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Specifications
MC9328MX21 Product Preview, Rev. 1.1
Freescale Semiconductor
21
3.7
External DMA Request and Grant
The External DMA request is an active low signal to be used by devices external to i.MX21 processor to request
the DMAC for data transfer.
After assertion of External DMA request the DMA burst will start when the channel on which the External request
is the source (as per the RSSR settings) becomes the current highest priority channel. The external device using the
External DMA request should keep its request asserted until it is serviced by the DMAC. One External DMA
request will initiate one DMA burst.
The output External Grant signal from the DMAC is an active-low signal.When the following conditions are true,
the External DMA Grant signal is asserted with the initiation of the DMA burst.
The DMA channel for which the DMA burst is ongoing has request source as external DMA Request (as
per source select register setting).
REN and CEN bit of this channel are set.
External DMA Request is asserted.
After the grant is asserted, the External DMA request will not be sampled until completion of the DMA burst. As
the external request is synchronized, the request synchronization will not be done during this period. The priority of
the external request becomes low for the next consecutive burst, if another DMA request signal is asserted.
Worst case—that is, the smallest burst (1 byte read/write) timing diagrams are shown in Figure 4 and Figure 5 on
page 21. Minimum and maximum timings for the External request and External grant signals are present in
Figure 4 shows the minimum time for which the External Grant signal remains asserted when an External DMA
request is de-asserted immediately after sensing grant signal active.
Figure 4. Assertion of DMA External Grant Signal
Figure 5 shows the safe maximum time for which External DMA request can be kept asserted, after sensing grant
signal active such that a new burst is not initiated.
Figure 5. Safe Maximum Timings for External Request De-Assertion
Ext_DMAReq
Ext_DMAGrant
tmin_assert
Ext_DMAReq
Data read from
External device
Data written to
External device
Ext_DMAGrant
tmax_write
tmax_read
tmax_req_assert
NOTE: Assuming in worst case the data is read/written from/to External device as per the above waveform.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC9328MX21CVK | 功能描述:處理器 - 專門應(yīng)用 DB I.MX21 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21CVK | 制造商:Freescale Semiconductor 功能描述:Microcontroller |
| MC9328MX21CVKR2 | 功能描述:處理器 - 專門應(yīng)用 DB I.MX21 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21CVM | 功能描述:處理器 - 專門應(yīng)用 DB I.MX21 17X17 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21CVM | 制造商:Freescale Semiconductor 功能描述:Microprocessor |
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