參數(shù)資料
型號: MC9328MX21CJM
廠商: Freescale Semiconductor
文件頁數(shù): 12/100頁
文件大?。?/td> 0K
描述: MPU I.MX21 289-MAPBGA
特色產(chǎn)品: MC9328MX21 Multimedia Processor
標準包裝: 90
系列: i.MX21
核心處理器: ARM9
芯體尺寸: 32-位
速度: 266MHz
連通性: 1 線,EBI/EMI,I²C,IrDA,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外圍設備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 192
程序存儲器類型: ROMless
電壓 - 電源 (Vcc/Vdd): 1.45 V ~ 3.3 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 289-LFBGA
包裝: 托盤
產(chǎn)品目錄頁面: 732 (CN2011-ZH PDF)
Specifications
MC9328MX21 Technical Data, Rev. 3.4
Freescale Semiconductor
19
Figure 3. Timing Relationship with RESET_IN
3.7
External DMA Request and Grant
The External DMA request is an active low signal to be used by devices external to i.MX21 processor to
request the DMAC for data transfer.
After assertion of External DMA request the DMA burst will start when the channel on which the External
request is the source (as per the RSSR settings) becomes the current highest priority channel. The external
device using the External DMA request should keep its request asserted until it is serviced by the DMAC.
One External DMA request will initiate one DMA burst.
Table 12. Reset Module Timing Parameters
Ref
No.
Parameter
1.8 V
± 0.10 V 3.0 V ± 0.30 V
Unit
Min
Max
Min
Max
1
Width of input POWER_ON_RESET
800
800
ms
2
Width of internal POWER_ON_RESET
(CLK32 at 32 kHz)
300
ms
3
7k to 32k-cycle stretcher for SDRAM reset
7
Cycles of CLK32
4
14k to 32k-cycle stretcher for internal system reset HRESERT
and output reset at pin RESET_OUT
14
Cycles of CLK32
5
Width of external hard-reset RESET_IN
4
4
Cycles of CLK32
6
4k to 32k-cycle qualifier
4
Cycles of CLK32
14 cycles @ CLK32
RESET_IN
CLK32
HCLK
5
4
HRESET
RESET_OUT
6
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