參數(shù)資料
型號(hào): MC9328MX1VM20R2
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 56/100頁(yè)
文件大?。?/td> 0K
描述: IC MCU I.MX 200MHZ 256-MAPBGA
標(biāo)準(zhǔn)包裝: 1,000
系列: i.MX1
核心處理器: ARM9
芯體尺寸: 32-位
速度: 200MHz
連通性: EBI/EMI,I²C,MMC,智能卡,SPI,SSI,UART/USART,USB
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 110
程序存儲(chǔ)器類型: ROMless
電壓 - 電源 (Vcc/Vdd): 1.7 V ~ 3.3 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 256-MAPBGA
包裝: 帶卷 (TR)
Functional Description and Application Information
MC9328MX1 Technical Data, Rev. 7
Freescale Semiconductor
59
4.4.4
Non-TFT Panel Timing
Figure 33. Non-TFT Panel Timing
4.5
Pen ADC Specifications
The specifications for the pen ADC are shown in Table 18 through Table 20.
Table 17. Non TFT Panel Timing Diagram
Symbol
Parameter
Allowed Register
Minimum Value1, 2
1 Maximum frequency of LCDC_CLK is 48 MHz, which is controlled by Peripheral Clock Divider Register.
2 Maximum frequency of SCLK is HCLK / 5, otherwise LD output will be wrong.
Actual Value
Unit
T1
HSYN to VSYN delay3
3 VSYN, HSYN and SCLK can be programmed as active high or active low. In the above timing diagram, all
these 3 signals are active high.
0HWAIT2+2
Tpix4
4 Tpix is the pixel clock period which equals LCDC_CLK period * (PCD + 1).
T2
HSYN pulse width
0
HWIDTH+1
Tpix
T3
VSYN to SCLK
0
≤ T3 ≤ Ts5
5 Ts is the shift clock period. Ts = Tpix * (panel data bus width).
T4
SCLK to HSYN
0
HWAIT1+1
Tpix
Table 18. Pen ADC System Performance
Full Range Resolution1
1 Tested under input = 0~1.8V at 25°C
13 bits
Non-Linearity Error1
4 bits
Accuracy 1
9 bits
T1
T2
T4
T3
XMAX
VSYN
SCLK
HSYN
LD[15:0]
T2
T1
Ts
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