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| 型號(hào)： | MC9328MX1VM20R2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA256 |
| 封裝： | 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MAPBGA-256 |
| 文件頁數(shù)： | 26/100頁 |
| 文件大?。?/td> | 1267K |
| 代理商： | MC9328MX1VM20R2 |
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Functional Description and Application Information
MC9328MX1 Technical Data, Rev. 7
Freescale Semiconductor
31
4.4.2.1
WAIT Read Cycle without DMA
Figure 6. WAIT Read Cycle without DMA
Table 13. WAIT Read Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
Number
Characteristic
3.0 ± 0.3 V
Unit
Minimum
Maximum
1OE and EB assertion time
See note 2
–
ns
2CS5 pulse width
3T
–
ns
3OE negated to address inactive
56.81
–
ns
4
Wait asserted after OE asserted
–
1020T
ns
5
Wait asserted to OE negated
2T+2.2
3T+7.17
ns
6
Data hold timing after OE negated
T-1.86
–
ns
7
Data ready after wait asserted
0
T
ns
8
OE negated to CS negated
1.5T+0.24
1.5T+0.85
ns
9
OE negated after EB negated
0.5
1.5
ns
10
Become low after CS5 asserted
0
1019T
ns
11
Wait pulse width
1T
1020T
ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when
EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
WAIT
Address
EB
CS5
OE
DATABUS
programmable
min 0ns
1
2
3
8
9
5
6
7
11
10
4
X1)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX1
Product
Family
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