參數(shù)資料
型號(hào)： MC9328MX1VM15R2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256
封裝： 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MAPBGA-256
文件頁數(shù)： 27/100頁
文件大?。?/td> 1267K
代理商： MC9328MX1VM15R2
Functional Description and Application Information
MC9328MX1 Technical Data, Rev. 7
32
Freescale Semiconductor
4.4.2.2
WAIT Read Cycle DMA Enabled
Figure 7. DTACK WAIT Read Cycle DMA Enabled
Table 14. DTACK WAIT Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
Number
Characteristic
3.0 ± 0.3 V
Unit
Minimum
Maximum
1OE and EB assertion time
See note 2
–
ns
2CS pulse width
3T
–
ns
3OE negated before CS5 is negated
1.5T+0.24
1.5T+0.85
ns
4
Address inactived before CS negated
–
0.93
ns
5
Wait asserted after CS5 asserted
–
1020T
ns
6Wait asserted to OE negated
2T+2.2
3T+7.17
ns
7
Data hold timing after OE negated
T-1.86
–
ns
8
Data ready after wait is asserted
–
T
ns
9CS deactive to next CS active
T
–
ns
10
OE negate after EB negate
0.5
1.5
ns
11
Wait becomes low after CS5 asserted
0
1019T
ns
RW
WAIT
Address
EB
CS5
OE
(logic high)
DATABUS
programmable
min 0ns
1
2
3
8
9
5
6
7
11
10
12
4
nput to
MX1)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX1
Product
Family
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