參數(shù)資料
型號: MC9328MX1CVH15
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 150 MHz, RISC PROCESSOR, PBGA256
封裝: 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, MAPBGA-256
文件頁數(shù): 56/96頁
文件大小: 1486K
代理商: MC9328MX1CVH15
MC9328MX1 Advance Information, Rev. 4.1
6
Freescale Semiconductor
Signals and Connections
2 Signals and Connections
Table 3 identifies and describes the MC9328MX1 signals that are assigned to package pins. The signals are
grouped by the internal module that they are connected to.
Table 3. Signal Names and Descriptions
Signal Name
Function/Notes
External Bus/Chip Select (EIM)
A [24:0]
Address bus signals
D [31:0]
Data bus signals
EB0
MSB Byte Strobe—Active low external enable byte signal that controls D [31:24]
EB1
Byte Strobe—Active low external enable byte signal that controls D [23:16]
EB2
Byte Strobe—Active low external enable byte signal that controls D [15:8]
EB3
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0]
OE
Memory Output Enable—Active low output enables external data bus
CS [5:0]
Chip Select—The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by
the Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected.
ECB
Active low input signal sent by flash device to the EIM whenever the flash device must terminate an
on-going burst sequence and initiate a new (long first access) burst sequence.
LBA
Active low signal sent by flash device causing the external burst device to latch the starting burst
address.
BCLK (burst clock)
Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW
RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE
input signal by external DRAM.
Bootstrap
BOOT [3:0]
System Boot Mode Select—The operational system boot mode of the MC9328MX1 upon system
reset is determined by the settings of these pins.
SDRAM Controller
SDBA [4:0]
SDRAM/SyncFlash non-interleave mode bank address multiplexed with address signals A [15:11].
These signals are logically equivalent to core address p_addr [25:21] in SDRAM/SyncFlash cycles.
SDIBA [3:0]
SDRAM/SyncFlash interleave addressing mode bank address multiplexed with address signals A
[19:16]. These signals are logically equivalent to core address p_addr [12:9] in SDRAM/SyncFlash
cycles.
MA [11:10]
SDRAM address signals
MA [9:0]
SDRAM address signals which are multiplex with address signals A [10:1]. MA [9:0] are selected on
SDRAM/SyncFlash cycles.
相關PDF資料
PDF描述
MC9328MX1VH20 200 MHz, RISC PROCESSOR, PBGA256
MC9328MX1VH15 150 MHz, MICROPROCESSOR, PBGA256
MC9328MX1VM15 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256
MC9328MX1CVM15R2 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256
MC9328MX1VM20R2 32-BIT, 200 MHz, RISC PROCESSOR, PBGA256
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