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參數(shù)資料
| 型號(hào)： | MC92501GC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM Cell Processor |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA256 |
| 封裝： | GTBGA-256 |
| 文件頁(yè)數(shù)： | 1/52頁(yè) |
| 文件大?。?/td> | 283K |
| 代理商： | MC92501GC |
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MC92501
1
Motorola, Inc. 1998
Order this document
by MC92501/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
ATM Cell Processor
The ATM Cell Processor (MC92501) is an Asynchronous Transfer Mode (ATM)
layer device composed of dedicated high-performance ingress and egress cell
processors combined with UTOPIA Level 2-compliant physical (PHY) and switch
interface ports (see Block Diagram). The MC92501 is a second generation ATM
cell processor in Motorolas 92500 series. This document provides information
on the new features offered by the second generation ATM cell processor. This
document, combined with MC92500/D, provides the complete speciTcation for
the ATM cell processor.
New Features of the MC92501:
￥
Implements ATM Layer Functions for Broadband ISDN According to ATM
Forum UNI 4.0 and TM 4.0 SpeciTcations, ITU Recommendations, and
Bellcore Recommendations
Provides ABR Relative Rate Marking and EFCI Marking According to TM 4.0
Selective Discard CLP = 1 (or CLP = 0+1) Flow on Selected Connections
UTOPIA Level 2 PHY Interface and UTOPIA ATM Layer Interface
Supports Both Partial Packet Discard (PPD) and Early Packet Discard (EPD)
Change ABR RM Cell Priority
Support for CLP Transparency
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Existing MC92500 Features:
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Full-Duplex Operation at Data Rates up to 155 Mbit/sec
Performs Internal VPI and VCI Address Compression for up to 64K VCs
CLP-Aware Peak, Average, and Burst-Length Policing with Programmable
Tag/Drop Action Per Policer
Supports up to 16 Physical Links Using Dedicated Ingress/Egress MultiPHY
Control Signals
Each Physical Link Can Be ConTgured as Either a UNI or NNI Port
Supports Multicast, Multiport Address Translation
Maintains Both Virtual Connection and Physical Link Counters on Both
Ingress and Egress Cell Flows
Provides a Flexible 32-Bit External Memory Port for Context Management
Automated AIS, RDI, CC, and Loopback Functions with Performance
Monitoring Block Test on All 64K Connections
Programmable 32-Bit Microprocessor Interface Supporting Big-Endian or
Little-Endian Bus Formats
Bidirectional UPC or NPC Design with up to Four Leaky Buckets Per
Connection
Supports a Programmable Number of Additional Switch Overhead
Parameters Allowing Adaptation to Any Switch Routing Header Format
Provides Per-Link Cell Counters in Both Directions
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This document contains information on a new product. SpeciTcations and information herein are subject to change without notice.
MC92501
ORDERING INFORMATION
MC92501GC
GTBGA
GC SUFFIX
GTBGA
CASE 1208
REV 1.2
2/98
TN98020500
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