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參數(shù)資料
| 型號： | P83CL882 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 Ultra Low Power ULP telephony controller |
| 中文描述： | 80C51的超低功耗無鉛汽油電話控制器 |
| 文件頁數(shù)： | 10/88頁 |
| 文件大小： | 328K |
| 代理商： | P83CL882 |
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2001 Jun 19
10
Philips Semiconductors
Product specification
80C51 Ultra Low Power (ULP) telephony controller
P83CL882
6.1.3
O
N
-
CHIP CLOCKS
The microcontroller does not need a clock signal to run
instructions, because the CPU is built using the Philips
exclusive handshake technology. The peripheral blocks
however are connected to a clock for synchronization with
theoutsideworld(e.g.MSK)orforatimedapplication(e.g.
Timer 2). The block related SFRs (peripheral function) are
therefore updated/modified with the applied clock. Two
prescalers (PSC1 and PSC2) are implemented which
allow the generation of two programmable clock signals
f
psc
and f
per
for internal usage.
Signal f
psc
from PSC1 is the default input clock of the timer
blocks. The complete timer functionality is specified in the
Section 6.5. Connected timers are the three 16-bit
timers Timer 0, 1 and 2 and the 8-bit Watchdog Timer.
The time interval of the connected timers can be adjusted
by programming of PSC1. The output frequency f
psc
can
be changed by selecting the division factor with the bits
PRESC.[2:0], (see Table 7).
All peripheral blocks, which require a clock signal: MSK,
and I
2
C-bus interface are connected to the clock signal
f
per
. PSC2 can be programmed by setting bits PRESC.4
and PRESC.3 (see Table 7). The choice of the division
factor must guarantee that all of the peripheral blocks are
within their specification, specially if an external clock
source of up to 12 MHz is applied.
Additionally Timer 1 and Timer 0 have a multiplexer on the
clock input to choose from 4 different clock sources.
The multiplexers are switched by setting user controllable
bits in the SYSCON SFR (bits 7 to 4). In the default setting
both timers are incrementing on the clock signal f
psc
comingfromPSC1.Timer 1andTimer 0canhoweveralso
run on clock signal f
per
coming from PSC2. If used in the
proper way this flexibility on the timer input sources can
substantially contribute to a decrease in power
consumption. Ideas and tipsto reducepower consumption
are given in Chapter 9.
The clock source of Timer 1 and Timer 0 can also be
switched to an external clock input signal T1 or T0 which
are multiplexed with one of the device input pins.
This mode is also functional even when there is no system
clock available. This means when a clock source is
supplied on a port pin Timer 1 or Timer 0 can count and
generate interrupts even when the chip is in Power-down
mode. More details are specified in Section 6.5.
The last multiplexer input to Timer 1 and Timer 0 is an
auxiliary mode which can be used to obtain the operation
speed from the handshake CPU. If this mode is activated
for the Timer 1 input source, the timer increments on every
ROM request. This means the timer increments by three
for a three byte instruction and by two for a two byte
instructionetc.IftheauxiliarymodeisactivatedforTimer 0
the timer increments on every instruction executed by
the CPU. This means the timer register holds the number
of instructions executed in a certain time frame. More
ideas and tips on how these clock source modes can be
used together with the handshake CPU can be found in
Chapter 9.
Table 3
Bits T1SRC[1:0] are defined in SYSCON SFR.
Timer 1 input source select modes
Table 4
Bits T0SRC[1:0] are defined in SYSCON SFR.
Timer 0 input source select modes
T1SRC1
T1SRC0
DESCRIPTION
0
0
1
0
1
0
f
psc
is the Timer 1 clock input
T1 is the Timer 1 clock input
the ROMreq signal is the Timer 1
clock input
f
per
is the Timer 1 clock input
1
1
T0SRC1
T0SRC0
DESCRIPTION
0
0
1
0
1
0
f
psc
is the Timer 0 clock input
T0 is the Timer 0 clock input
the InstrReq signal is the Timer 0
clock input
f
per
is the Timer 0 clock input
1
1
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