LVI Interrupts
MC68HC908QL4 Data Sheet, Rev. 7
Freescale Semiconductor
99
10.4 LVI Interrupts
The LVI module does not generate interrupt requests.
10.5 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby modes.
10.5.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can
generate a reset and bring the MCU out of wait mode.
10.5.2 Stop Mode
If the LVIPWRD bit in the configuration register is cleared and the LVISTOP bit in the configuration
register is set, the LVI module remains active. If enabled to generate resets, the LVI module can generate
a reset and bring the MCU out of stop mode.
10.6 Registers
The LVI status register (LVISR) contains a status bit that is useful when the LVI is enabled and LVI reset
is disabled.
LVIOUT — LVI Output Bit
This read-only flag becomes set when the VDD voltage falls below the VTRIPF trip voltage and is cleared
Bit 76
5
4
3
2
1Bit 0
Read:
LVIOUT
0
000
0
R
Write:
Reset:
0
000
00
= Unimplemented
R
= Reserved
Figure 10-2. LVI Status Register (LVISR)
Table 10-1. LVIOUT Bit Indication
VDD
LVIOUT
VDD > VTRIPR
0
VDD < VTRIPF
1
VTRIPF < VDD < VTRIPR
Previous value
