Memory
MC68HC908GR16 Data Sheet, Rev. 5.0
32
Freescale Semiconductor
$001E
Configuration Register 2
(CONFIG2)(1)
Read:
0000
R
TMBCLK-
SEL
OSCENIN-
STOP
ESCIBD-
SRC
Write:
Reset:
0000000
1
$001F
Configuration Register 1
(CONFIG1)(1)
Read:
COPRS
LVISTOP
LVIRSTD
LVIPWRD
LVI5OR3
(Note 1)
SSREC
STOP
COPD
Write:
Reset:
0000000
0
1. One-time writable register after each reset, except LVI5OR3 bit. LVI5OR3 bit is only reset via POR (power-on reset).
$0020
Timer 1 Status and Control
Register (T1SC)
Read:
TOF
TOIE
TSTOP
00
PS2
PS1
PS0
Write:
0
TRST
Reset:
0010000
0
$0021
Timer 1 Counter
Register High (T1CNTH)
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
0000000
0
$0022
Timer 1 Counter
Register Low (T1CNTL)
Read:
Bit 7
654321
Bit 0
Write:
Reset:
0000000
0
$0023
Timer 1 Counter Modulo
Register High (T1MODH)
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
1111111
1
$0024
Timer 1 Counter Modulo
Register Low (T1MODL)
Read:
Bit 7
654321
Bit 0
Write:
Reset:
1111111
1
$0025
Timer 1 Channel 0 Status and
Control Register (T1SC0)
Read:
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
Write:
0
Reset:
0000000
0
$0026
Timer 1 Channel 0
Register High (T1CH0H)
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
Indeterminate after reset
$0027
Timer 1 Channel 0
Register Low (T1CH0L)
Read:
Bit 7
654321
Bit 0
Write:
Reset:
Indeterminate after reset
$0028
Timer 1 Channel 1 Status and
Control Register (T1SC1)
Read:
CH1F
CH1IE
0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
Write:
0
Reset:
0000000
0
Addr.
Register Name
Bit 7
654321
Bit 0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 8)