
MC68HC908EY16A MC68HC908EY8A Data Sheet, Rev. 2
64
Freescale Semiconductor
COPRS — COP Rate Select Bit
1 = COP timeout period = 8176 CGMXCLK cycles
0 = COP timeout period = 262,128 CGMXCLK cycles
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.
Reset clears LVISTOP.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bit
1 = LVI module resets disabled
0 = LVI module resets enabled
LVIPWRD — LVI Power Disable Bit
1 = LVI module power disabled
0 = LVI module power enabled
LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit
(LVI) Module. The voltage mode selected for the LVI will typically be 5 V. However, users may choose
trip points for each of the modes.
1 = LVI operates in 5-V mode.
0 = LVI operates in 3-V mode.
NOTE
The LVI5OR3 bit is cleared by a power-on reset (POR) only. Other resets
will leave this bit unaffected.
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a
4096-CGMXCLK cycle delay.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLCK cycles
NOTE
Exiting stop mode by an LVI reset will result in the long stop recovery.
Address:
$001F
Bit 7
654321
Bit 0
Read:
COPRS
LVISTOP
LVIRSTD
LVIPWRD LVI5OR3(1)
SSREC
STOP
COPD
Write:
Reset:
00000000
1. The LVI5OR3 bit is cleared only by a power-on reset (POR).
Figure 5-1. Configuration Register 1 (CONFIG1)