
Low Voltage Inhibit (LVI)
LVI Status Register
MC68HC908AZ60A — Rev 2.0
Technical Data
MOTOROLA
Low Voltage Inhibit (LVI)
233
16.5 LVI Status Register
The LVI status register flags VDD voltages below the LVITRIPF level.
LVIOUT — LVI Output Bit
This read-only flag becomes set when the VDD voltage falls below the
LVITRIPF voltage for 32 to 40 CGMXCLK cycles. (See Table 16-1). Reset clears the LVIOUT bit.
16.6 LVI Interrupts
The LVI module does not generate interrupt requests.
Address:
$FE0F
Bit 7
654321
Bit 0
Read:
LVIOUT
0000000
Write:
Reset:
00000000
= Unimplemented
Figure 16-3. LVI Status Register (LVISR)
Table 16-1. LVIOUT Bit Indication
VDD
LVIOUT
At Level:
For Number of
CGMXCLK Cycles:
VDD > LVITRIPR
Any
0
VDD < LVITRIPF
< 32 CGMXCLK Cycles
0
VDD < LVITRIPF
Between 32 and 40
CGMXCLK Cycles
0 or 1
VDD < LVITRIPF
> 40 CGMXCLK Cycles
1
LVITRIPF < VDD < LVITRIPR
Any
Previous Value