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參數(shù)資料
| 型號： | MC88913D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW SKEW CMOS CLOCK DRIVER |
| 中文描述： | 88913 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 2 INVERTED OUTPUT(S), PDSO14 |
| 封裝： | PLASTIC, SOIC-14 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 75K |
| 代理商： | MC88913D |
MC88913
TIMING SOLUTIONS
BR1333 — REV 5
3
MOTOROLA
DC CHARACTERISTICS
TA = +25
°
C
TA =
–40 to +85
°
C
Symbol
Parameter
VCC
Typ
Guaranteed Max
Unit
Conditions
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
VOUT = 0.1V or
VCC – 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
VOUT = 0.1V or
VCC – 0.1V
IOUT = –50
μ
A
VOH
Minimum High Level
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
V
4.5
5.5
3.86
4.86
3.76
4.76
V
*VIN = VIL or VIH
IOH = –24mA
–24mA
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
V
IOUT = 50
μ
A
4.5
5.5
0.36
0.36
0.44
0.44
V
*VIN = VIL or VIH
IOH = 24mA
24mA
IIN
Maximum Input
5.5
±
0.1
±
0.1
μ
A
VI = VCC, GND
ICCT
Maximum ICC/Input
5.5
0.6
1.5
mA
VI = VCC –2.1V
IOLD
Minimum Dynamic Output Current**
5.5
75
mA
VOLD = 1.65V
IOHD
5.5
–75
mA
VOHD = 3.85V
* All outputs loaded; thresholds on inputs associated with output under test.
** Maximum test duration 20ms, one output at a time.
AC CHARACTERISTICS
(VCC = 5.0V
±
10%)
TA = 25
°
C
CL = 50 pF
TA = –40 to +85
°
C
CL = 50 pF
Symbol
Parameter
VCC (V)
Min
Max
Min
Max
Unit
fMAX
Maximum Clock Frequency (50% Duty Cycle)
5.0
110
110
MHz
tPLH,
tPHL
Propagation Delay
CLK to Qn, Qn
5.0
4.0
10.5
4.0
11.5
ns
tPV
Propagation Delay Variation
CLK to Q0, Q1, Q2 (see Note 1)
5.0
4.0
5.0
ns
Propagation Delay Variation
CLK to All Outputs (see Note 1)
5.0
4.5
5.5
ns
tPS
Propagation Delay Skew (Q0, Q1, Q2)
|tPHL Actual – tPLH Actual|
5.0
1.0
1.0
ns
Propagation Delay Skew (All Outputs)
|tPHL Actual – tPLH Actual|
5.0
1.5
1.5
ns
tOS
Output–to–Output Skew (Q0, Q1, Q2)
|tp Qn – tp Qm| (see Note 2)
5.0
1.0
1.0
ns
Output–to–Output Skew (All Outputs)
|tp Qn – tp Qm| (see Note 2)
5.0
1.5
1.5
ns
trise
tfall
Rise/Fall Time for Q0, Q1, Q2
(0.2 x VCC to 0.8 x VCC)
5.0
3.0
4.0
ns
Rise/Fall Time for All Outputs
(0.2 x VCC to 0.8 x VCC)
5.0
3.5
4.5
ns
1. For a given set of conditions (i.e., capacitive load, temperature and VCC) the variation from device to device is guaranteed to be less than or equal to the maximum.
2. Where tp Qn and tp Qm are the actual propagation delays (any combination of HIGH or LOW) for any two separate outputs from a given high transition of CLK.
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