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參數(shù)資料
| 型號： | MC8641VU1250JC |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, ROHS COMPLIANT, CERAMIC, BGA-1023 |
| 文件頁數(shù)： | 15/140頁 |
| 文件大?。?/td> | 1484K |
| 代理商： | MC8641VU1250JC |
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MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
111
Clocking
18.2
MPX to SYSCLK PLL Ratio
The MPX clock is the clock that drives the MPX bus, and is also called the platform clock. The frequency
of the MPX is set using the following reset signals, as shown in Table 68:
SYSCLK input signal
Binary value on LA[28:31] at power up
Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note
that the DDR data rate is the determining factor in selecting the MPX bus frequency, since the MPX
frequency must equal the DDR data rate.
Table 66. Platform/MPX bus Clocking Specifications
Characteristic
Maximum Processor Core
Frequency
Unit
Notes
1000, 1250, 1333, 1500MHz
Min
Max
Platform/MPX bus clock frequency
400
500-600
MHz
1, 2
Notes:
1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be
chosen such that the resulting SYSCLK frequency, e600 (core) frequency, and MPX clock
frequency do not exceed their respective maximum or minimum operating frequencies. Refer to
ratio settings.
2. Platform/MPX frequencies between 400 and 500 MHz are not supported.
Table 67. Local Bus Clocking Specifications
Characteristic
Maximum Processor Core
Frequency
Unit
Notes
1000, 1250, 1333, 1500MHz
Min
Max
Local bus clock speed (for Local Bus
Controller)
25
133
MHz
1
Notes:
1. The Local bus clock speed on LCLK[0:2] is determined by MPX clock divided by the Local Bus
PLL ratio programmed in LCRR[CLKDIV]. See the reference manual for the MPC8641D for more
information on this.
Table 68. MPX:SYSCLK Ratio
Binary Value of
LA[28:31]
Signals
MPX:SYSCLK Ratio
0000
Reserved
0001
Reserved
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