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參數(shù)資料
型號(hào)： MC8641DTVU1250HE
廠商： Freescale Semiconductor
文件頁數(shù)： 26/130頁
文件大小： 0K
描述： IC MPU DUAL CORE E600 1023FCCBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.25GHz
電壓： 1.05V
安裝類型： 表面貼裝
封裝/外殼： 1023-BCBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 1023-FCCBGA（33x33）
包裝： 托盤
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
121
System Design Information
SDn_TX[7:0]
The following pins must be connected to GND:
SDn_RX[7:0]
SDn_REF_CLK
SDn_REF_CLK
NOTE
It is recommended to power down the unused lane through SRDS1CR1[0:7]
register (offset = 0xE_0F08) and SRDS2CR1[0:7] register
(offset = 0xE_0F44.) (This prevents the oscillations and holds the receiver
output in a fixed state.) that maps to SERDES lane 0 to lane 7 accordingly.
For other directions on reserved or no-connects pins see Section 17, “Signal Listings.”
20.6
Pull-Up and Pull-Down Resistor Requirements
The MPC8641 requires weak pull-up resistors (2–10 k
Ω is recommended) on all open drain type pins.
The following pins must NOT be pulled down during power-on reset: TSEC4_TXD[4], LGPL0/LSDA10,
LGPL1/LSDWE, TRIG_OUT/READY, and D1_MSRCID[2].
The following are factory test pins and require strong pull up resistors (100
Ω –1 kΩ) to OVDD
LSSD_MODE, TEST_MODE[0:3].The following pins require weak pull up resistors (2–10 k
Ω) to their
specific power supplies: LCS[0:4], LCS[5]/DMA_DREQ2, LCS[6]/DMA_DACK[2],
LCS[7]/DMA_DDONE[2], IRQ_OUT, IIC1_SDA, IIC1_SCL, IIC2_SDA, IIC2_SCL, and
CKSTP_OUT.
The following pins should be pulled to ground with a 100-
Ω resistor: SD1_IMP_CAL_TX,
SD2_IMP_CAL_TX. The following pins should be pulled to ground with a 200-
Ω resistor:
SD1_IMP_CAL_RX, SD2_IMP_CAL_RX.
TSECn_TX_EN signals require an external 4.7-k
Ω pull down resistor to prevent PHY from seeing a valid
Transmit Enable before it is actively driven.
When the platform frequency is 400 MHz, TSEC1_TXD[1] must be pulled down at reset.
TSEC2_TXD[4] and TSEC2_TX_ER pins function as cfg_dram_type[0 or 1] at reset and MUST BE
VALID BEFORE HRESET ASSERTION when coming out of device sleep mode.
20.6.1
Special instructions for Single Core device
The mechanical drawing for the single core device does not have all the solder balls that exist on the single
core device. This includes all the balls for VDD_Core1 and SENSEVDD_Core1 which exist on the
package for the dual core device, but not on the single core package. A solder ball is present for
SENSEVSS_Core1 and needs to be connected to ground with a weak (2-10 kΩ) pull down resistor.
Likewise, AVDD_Core1 needs to be pulled to ground as shown in Figure 64.
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