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| 型號： | MC8641DTVU1000GE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 40/130頁 |
| 文件大小： | 0K |
| 描述： | IC MPU DUAL CORE E600 1023FCCBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MPC86xx |
| 處理器類型： | 32-位 MPC86xx PowerPC |
| 速度： | 1.0GHz |
| 電壓： | 1.05V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 1023-BCBGA，F(xiàn)CCBGA |
| 供應(yīng)商設(shè)備封裝： | 1023-FCCBGA（33x33） |
| 包裝： | 托盤 |
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MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
17
Input Clocks
4
Input Clocks
Table 7 provides the system clock (SYSCLK) DC specifications for the MPC8641.
4.1
System Clock Timing
Table 8 provides the system clock (SYSCLK) AC timing specifications for the MPC8641.
4.1.1
SYSCLK and Spread Spectrum Sources
Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference
emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise
magnitude in order to meet industry and government requirements. These clock sources intentionally add
long-term jitter in order to diffuse the EMI spectral content. The jitter specification given in Table 8
considers short-term (cycle-to-cycle) jitter only and the clock generator’s cycle-to-cycle output jitter
Table 7. SYSCLK DC Electrical Characteristics (OVDD = 3.3 V ± 165 mV)
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2OVDD + 0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
Input current
(VIN
1 = 0 V or V
IN = VDD)
IIN
—±5
μA
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
Table 8. SYSCLK AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
SYSCLK frequency
fSYSCLK
66
—
166.66
MHz
1
SYSCLK cycle time
tSYSCLK
6—
—
ns
—
SYSCLK rise and fall time
tKH, tKL
0.61.0
1.2ns
2
SYSCLK duty cycle
tKHK/tSYSCLK
40
—
60
%
3
SYSCLK jitter
—
150
ps
4, 5
Notes:
1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the
resulting SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective
maximum or minimum operating frequencies. See Section 18.2, “MPX to SYSCLK PLL Ratio,” and Section 18.3,
“e600 to MPX clock PLL Ratio,” for ratio settings.
2. Rise and fall times for SYSCLK are measured at 0.4 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the short term jitter only and is guaranteed by design.
5. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter. Note that the
frequency modulation for SYSCLK reduces significantly for the spread spectrum source case. This is to guarantee
what is supported based on design.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC8641DTVU1000H | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications Addendum for the MC8641xTxxnnnnxC Series |
| MC8641DTVU1000J | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications Addendum for the MC8641xTxxnnnnxC Series |
| MC8641DTVU1000N | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications Addendum for the MC8641xTxxnnnnxC Series |
| MC8641DTVU1000NC | 功能描述:微處理器 - MPU G8,REV2.1 0.95V,-40/105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC8641DTVU1250G | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications Addendum for the MC8641xTxxnnnnxC Series |
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