MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
119
System Design Information
designer place at least one decoupling capacitor at each OVDD, Dn_GVDD, LVDD, TVDD, VDD_Coren,
and VDD_PLAT pin of the device. These decoupling capacitors should receive their power from separate
OVDD, Dn_GVDD, LVDD, TVDD, VDD_Coren, and VDD_PLAT and GND power planes in the PCB,
utilizing short traces to minimize inductance. Capacitors may be placed directly under the device using a
standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 F. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the OVDD, Dn_GVDD, LVDD, TVDD, VDD_Coren, and VDD_PLAT planes, to enable quick
recharging of the smaller chip capacitors. They should also be connected to the power and ground planes
through two vias to minimize inductance. Suggested bulk capacitors—100–330 F (AVX TPS tantalum
or Sanyo OSCON).
20.4
SerDes Block Power Supply Decoupling Recommendations
The SerDes block requires a clean, tightly regulated source of power (SVDD and XVDD_SRDSn) to ensure
low jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is
outlined below.
Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections
from all capacitors to power and ground should be done with multiple vias to further reduce inductance.
First, the board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible
to the supply balls of the device. Where the board has blind vias, these capacitors should be placed
directly below the chip supply and ground connections. Where the board does not have blind vias,
these capacitors should be placed in a ring around the device as close to the supply and ground
connections as possible.
Second, there should be a 1-F ceramic chip capacitor on each side of the device. This should be
done for all SerDes supplies.
Third, between the device and any SerDes voltage regulator there should be a 10-F, low
equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-F, low ESR SMT
tantalum chip capacitor. This should be done for all SerDes supplies.
20.5
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. In general all unused active low inputs should be tied to OVDD, Dn_GVDD, LVDD, TVDD,
VDD_Coren, and VDD_PLAT, XVDD_SRDSn, and SVDD as required and unused active high inputs should
be connected to GND. All NC (no-connect) signals must remain unconnected.
Special cases:
DDR - If one of the DDR ports is not being used the power supply pins for that port can be
connected to ground so that there is no need to connect the individual unused inputs of that port to
ground. Note that these power supplies can only be powered up again at reset for functionality to
occur on the DDR port. Power supplies for other functional buses should remain powered.