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| 型號(hào)： | MC8641DHX1500KE |
| 廠(chǎng)商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 70/130頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DUAL CORE PROCESSOR 1023-CBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MPC86xx |
| 處理器類(lèi)型： | 32-位 MPC86xx PowerPC |
| 速度： | 1.5GHz |
| 電壓： | 1.1V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 1023-BCBGA，F(xiàn)CCBGA |
| 供應(yīng)商設(shè)備封裝： | 1023-FCCBGA（33x33） |
| 包裝： | 托盤(pán) |
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MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
44
Freescale Semiconductor
Ethernet Management Interface Electrical Characteristics
Figure 23 provides the AC test load for eTSEC.
Figure 23. eTSEC AC Test Load
NOTE
Output will see a 50-
Ω load since what it sees is the transmission line.
Figure 24 shows the MII management AC timing diagram.
Figure 24. MII Management Interface Timing Diagram
MDIO to MDC hold time
tMDDXKH
0—
—
ns
—
MDC rise time
tMDCR
—
10
ns
4
MDC fall time
tMDHF
—
10
ns
4
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX
symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are
invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input
signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For
rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the system clock speed. (The maximum frequency is the maximum platform frequency
divided by 64.)
3. This parameter is dependent on the system clock speed. (That is, for a system clock of 267 MHz, the maximum frequency
is 8.3 MHz and the minimum frequency is 1.2 MHz; for a system clock of 375 MHz, the maximum frequency is 11.7 MHz
and the minimum frequency is 1.7 MHz.)
4. Guaranteed by design.
5. tMPXCLK is the platform (MPX) clock
Table 39. MII Management AC Timing Specifications (continued)
At recommended operating conditions with OVDD is 3.3 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
Notes
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
MDC
tMDDXKH
tMDC
tMDCH
tMDCR
tMDCF
tMDDVKH
tMDKHDX
MDIO
(Input)
(Output)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC8641DHX1500N | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8641DTHX1000G | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications Addendum for the MC8641xTxxnnnnxC Series |
| MC8641DTHX1000GC | 功能描述:微處理器 - MPU G8,REV2.1 1.05V,-40/105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線(xiàn)寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC8641DTHX1000H | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications Addendum for the MC8641xTxxnnnnxC Series |
| MC8641DTHX1000J | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications Addendum for the MC8641xTxxnnnnxC Series |
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