參數(shù)資料
型號： MC8640DTHX1250HE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1250 MHz, MICROPROCESSOR, CBGA1023
封裝： 33 X 33 MM, CERAMIC, FCBGA-1023
文件頁數(shù)： 110/130頁
文件大小： 1495K
代理商： MC8640DTHX1250HE
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
80
Freescale Semiconductor
Serial RapidIO
For each baud rate at which an LP-Serial transmitter is specified to operate, the output eye pattern of the
transmitter shall fall entirely within the unshaded portion of the transmitter output compliance mask shown
in Figure 54. This figure should be used with the parameters specified in Table 58 when measured at the
output pins of the device and the device is driving a 100-
Ω ± 5% differential resistive load. The output eye
pattern of an LP-Serial transmitter that implements pre-emphasis (to equalize the link and reduce
Table 56. Long Run Transmitter AC Timing Specifications—2.5 GBaud
Parameter
Symbol
Range
Unit
Notes
Min
Max
Output Voltage,
VO
–0.40
2.30
Volts
Voltage relative to COMMON of
either signal comprising a
differential pair
Differential Output Voltage
VDIFFPP
800
1600
mV p-p
—
Deterministic Jitter
JD
—0.17
UI p-p
—
Total Jitter
JT
—0.35
UI p-p
—
Multiple output skew
SMO
—
1000
ps
Skew at the transmitter output
between lanes of a multilane link
Unit Interval
UI
400
ps
± 100 ppm
Table 57. Long Run Transmitter AC Timing Specifications—3.125 GBaud
Parameter
Symbol
Range
Unit
Notes
Min
Max
Output Voltage,
VO
–0.40
2.30
Volts
Voltage relative to COMMON
of either signal comprising a
differential pair
Differential Output Voltage
VDIFFPP
800
1600
mV p-p
—
Deterministic Jitter
JD
—
0.17
UI p-p
—
Total Jitter
JT
—
0.35
UI p-p
—
Multiple output skew
SMO
—
1000
ps
Skew at the transmitter output
between lanes of a multilane
link
Unit Interval
UI
320
ps
± 100 ppm
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