參數(shù)資料
型號: MC8640DTHX1250HC
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1250 MHz, MICROPROCESSOR, CBGA1023
封裝: 33 X 33 MM, CERAMIC, FCBGA-1023
文件頁數(shù): 9/130頁
文件大小: 1495K
代理商: MC8640DTHX1250HC
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
106
Freescale Semiconductor
Clocking
Binary value on LA[28:31] at power up
Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note
that the DDR data rate is the determining factor in selecting the MPX bus frequency because the MPX
frequency must equal the DDR data rate.
18.3
e600 to MPX clock PLL Ratio
Table 69 describes the clock ratio between the platform and the e600 core clock. This ratio is determined
by the binary value of LDP[0:3], LA[27](cfg_core_pll[0:4] - reset config name) at power up, as shown in
18.4
Frequency Options
This section discusses the frequency options for the MPC8640.
Table 68. MPX:SYSCLK Ratio
Binary Value of
LA[28:31] Signals
MPX:SYSCLK Ratio
0000
Reserved
0001
Reserved
0010
2:1
0011
3:1
0100
4:1
0101
5:1
0110
6:1
0111
Reserved
1000
8:1
1001
Reserved
Table 69. e600 Core to MPX Clock Ratio
Binary Value of
LDP[0:3], LA[27] Signals
e600 core: MPX Clock Ratio
01000
2:1
01100
2.5:1
10000
3:1
11100
Reserved
10100
Reserved
01110
Reserved
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