參數(shù)資料
型號: MC8640DTHX1067NE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1067 MHz, MICROPROCESSOR, CBGA1023
封裝: 33 X 33 MM, CERAMIC, FCBGA-1023
文件頁數(shù): 115/130頁
文件大小: 1495K
代理商: MC8640DTHX1067NE
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
85
Serial RapidIO
15.8
Receiver Eye Diagrams
For each baud rate at which an LP-Serial receiver is specified to operate, the receiver shall meet the
corresponding bit error rate specification (Table 59 through Table 61) when the eye pattern of the receiver
test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the shown in
Figure 56 with the parameters specified in Table 62. The eye pattern of the receiver test signal is measured
at the input pins of the receiving device with the device replaced with a 100
Ω ± 5% differential resistive
load.
Figure 56. Receiver Input Compliance Mask
Table 62 shows the parameters for the receiver input compliance mask exclusive of sinusoidal jitter.
Table 62. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter
Receiver Type
VDIFFmin (mV)
VDIFFmax (mV)
A (UI)
B (UI)
1.25 GBaud
100
800
0.275
0.400
2.5 GBaud
100
800
0.275
0.400
3.125 GBaud
100
800
0.275
0.400
1
0
VDIFF max
–VDIFF max
VDIFF min
–VDIFF min
Time (UI)
Re
ce
iv
e
rDi
ff
e
re
n
ti
a
lI
n
p
u
tV
o
lt
a
g
e
0
AB
1-B
1-A
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