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參數(shù)資料
| 型號(hào)： | MC80C52TXXX-25SC |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CDIP40 |
| 文件頁(yè)數(shù)： | 54/109頁(yè) |
| 文件大?。?/td> | 10824K |
| 代理商： | MC80C52TXXX-25SC |
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34
AT32UC3A
10.3
Bus Matrix Connections
Accesses to unused areas returns an error result to the master requesting such an access.
The bus matrix has the several masters and slaves. Each master has its own bus and its own
decoder, thus allowing a different memory mapping per master. The master number in the table
below can be used to index the HMATRIX control registers. For example, MCFG0 is associated
with the CPU Data master interface.
Each slave has its own arbiter, thus allowing a different arbitration per slave. The slave number
in the table below can be used to index the HMATRIX control registers. For example, SCFG3 is
associated with the Internal SRAM Slave Interface.
Table 10-2.
Flash Memory Parameters
Part Number
Flash Size
(FLASH_PW)
Number of pages
(FLASH_P)
Page size
(FLASH_W)
General Purpose
Fuse bits
(FLASH_F)
AT32UC3A0512
512 Kbytes
1024
128 words
32 fuses
AT32UC3A1512
512 Kbytes
1024
128 words
32 fuses
AT32UC3A0256
256 Kbytes
512
128 words
32 fuses
AT32UC3A1256
256 Kbytes
512
128 words
32 fuses
AT32UC3A1128
128 Kbytes
256
128 words
32 fuses
AT32UC3A0128
128 Kbytes
256
128 words
32 fuses
Table 10-3.
High Speed Bus masters
Master 0
CPU Data
Master 1
CPU Instruction
Master 2
CPU SAB
Master 3
PDCA
Master 4
MACB DMA
Master 5
USBB DMA
Table 10-4.
High Speed Bus slaves
Slave 0
Internal Flash
Slave 1
HSB-PB Bridge 0
Slave 2
HSB-PB Bridge 1
Slave 3
Internal SRAM
Slave 4
USBB DPRAM
Slave 5
EBI
32058K
AVR32-01/12
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