參數(shù)資料
型號(hào)： MC80C52TXXX-20
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CDIP40
文件頁(yè)數(shù)： 549/586頁(yè)
文件大?。?/td> 25028K
代理商： MC80C52TXXX-20
65
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
...
;
0x1F036
jmp
SPM_RDY
; SPM Ready Handler
;
0x1F03E
RESET: ldi
r16,high(RAMEND); Main program start
0x1F03F
out
SPH,r16
; Set Stack Pointer to top of RAM
0x1F040
ldi
r16,low(RAMEND)
0x1F041
out
SPL,r16
0x1F042
sei
; Enable interrupts
0x1FO43
<instr>
xxx
12.2.1
Moving Interrupts Between Application and Boot Space
The General Interrupt Control Register controls the placement of the Interrupt Vector table.
12.3
Register description
12.3.1
MCUCR – MCU Control Register
Note:
1. Only available in the Atmel ATmega164PA/324PA/644PA/1284P.
Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash
memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot
Loader section of the Flash. The actual address of the start of the Boot Flash Section is deter-
mined by the BOOTSZ Fuses. Refer to the section ”Memory programming” on page 298 for
details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must
be followed to change the IVSEL bit:
a.
Write the Interrupt Vector Change Enable (IVCE) bit to one.
b.
Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled
in the cycle IVCE is set, and they remain disabled until after the instruction following the write to
IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status
Register is unaffected by the automatic disabling.
Note:
If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,
interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed
in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while
executing from the Boot Loader section. Refer to the section ”Memory programming” on page 298
for details on Boot Lock bits.
Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by
hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable
interrupts, as explained in the IVSEL description above. See the following Code Example.
Bit
7
654
3
2
1
0
JTD
BODS(1)
BODSE(1)
PUD
–
IVSEL
IVCE
MCUCR
Read/Write
R/W
R
R/W
Initial Value
0
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