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參數(shù)資料
| 型號： | MC80C52EXXX-16P883 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| 文件頁數(shù)： | 105/109頁 |
| 文件大?。?/td> | 10824K |
| 代理商： | MC80C52EXXX-16P883 |
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807
32117D–AVR-01/12
AT32UC3C
30.6.5
TDM Reception and Transmission Sequence
In Time Division Multiplexed (TDM) format, 1 to 8 data words are sent or received within each
frame, As in the I
2S protocol, data bits are left-adjusted in the channel time slot, with the MSB
transmitted first, starting one clock period after the transition on the Word Select line. Each time
slot is 32-bit long.
Figure 30-3. TDM Reception and Transmission Sequence
Data bits are sent on the falling edge of the Serial Clock and sampled on the rising edge of the
Serial Clock. The IWS pin provides a frame synchronization signal, starting one ISCK period
before the MSB of channel 0.
The Time Division Multiplexed (TDM) format is selected by writing a one to the MR.FORMAT
field.
The Frame Sync pulse can be either one ISCK period or one 32-bit time slot. This selection is
done by writing the MR.TDMFS bit.
The number of channels is selected by writing the MR.CHANNELS field.
The length of transmitted words can be chosen among 8, 16, 18, 20, 24, and 32 bits by writing
the MR.DATALENGTH field.
If the time slot allows for more data bits than programmed in the MR.DATALENGTH field, zeroes
are appended to the transmitted data word or extra received bits are discarded. If the time slot
allows for less data bits than programmed, the extra bits to be transmitted are not sent or the
missing bits are set to zero in the right-adjusted received data word.
30.6.6
Serial Clock and Word Select Generation
The generation of clocks in the IISC is described in Figure 30-4 on page 809.
In Slave mode, the Serial Clock and Word Select Clock are driven by an external master. ISCK
and IWS pins are inputs and no generic clock is required by the IISC.
In Master mode, the user can configure the Master Clock, Serial Clock, and Word Select Clock
through the Mode Register (MR). IMCK, ISCK, and IWS pins are outputs and a generic clock is
used to derive the IISC clocks.
Audio codecs connected to the IISC pins may require a Master Clock signal with a frequency
multiple of the audio sample frequency (fs), such as 256 fs. When the IISC is in Master mode,
writing a one to MR.IMCKMODE will output GCLK_IISC as Master Clock to the IMCK pin, and
will divide GCLK_IISC to create the internal bit clock, output on the ISCK pin. The clock division
factor is defined by writing to MR.IMCKFS and MR.DATALENGTH, as described ”IMCKFS:
Serial Clock (ISCK)
Frame sync (IWS)
Data (ISDI/ISDO)
Channel 0
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
Channel 2
Channel 1
Channel 3
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| MT80C51C-12R | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44 |
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