![](http://datasheet.mmic.net.cn/90000/MC80C32-20P883D_datasheet_2370675/MC80C32-20P883D_155.png)
155
XMEGA C3 [DATASHEET]
8492F–AVR–07/2013
33.5.14 SPI Characteristics
Figure 33-33.SPI timing requirements in master mode.
Figure 33-34.SPI timing requirements in slave mode.
MSB
LSB
B
S
L
B
S
M
tMOS
tMIS
tMIH
tSCKW
tSCK
tMOH
tSCKF
tSCKR
tSCKW
MO
SI
(Data Output)
MI
SO
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
MSB
LSB
B
S
L
B
S
M
tSIS
tSIH
tSSCKW
tSSCK
tSSH
tSOSSH
tSCKR
tSCKF
tSOS
tSSS
tSOSSS
MISO
(Data Output)
MOSI
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS