參數(shù)資料
型號: MC80C32-12
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 12 MHz, MICROCONTROLLER, CDIP40
封裝: 0.600 INCH, SIDE BRAZED, DIP-40
文件頁數(shù): 239/586頁
文件大小: 25028K
代理商: MC80C32-12
313
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
27.8
Serial downloading
Both the Flash and EEPROM memory arrays can be programmed using a serial programming
bus while RESET is pulled to GND. The serial programming interface consists of pins SCK,
MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction
needs to be executed first before program/erase operations can be executed. NOTE, in Table
27-15, the pin mapping for serial programming is listed. Not all packages use the SPI pins dedi-
cated for the internal Serial Peripheral Interface - SPI.
27.8.1
Serial Programming Pin Mapping
Figure 27-10. Serial programming and verify (1).
Notes:
1. If the device is clocked by the internal oscillator, it is no need to connect a clock source to the
XTAL1 pin.
2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8 - 5.5V.
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: >2 CPU clock cycles for f
ck <12MHz, 3 CPU clock cycles for fck 12MHz.
High: >2 CPU clock cycles for f
ck <12MHz, 3 CPU clock cycles for fck 12MHz.
Table 27-15. Pin mapping serial programming.
Symbol
Pins
(PDIP-40)
Pins
(TQFP/MLF-44)
I/O
Description
MOSI
PB5
I
Serial Data in
MISO
PB6
O
Serial Data out
SCK
PB7
I
Serial Clock
VCC
GND
XTAL1
SCK
MISO
MOSI
RESET
+1.8 - 5.5V
AVCC
+1.8 - 5.5V
(2)
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