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參數(shù)資料
| 型號： | MC80C0224K |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數(shù)： | 101/128頁 |
| 文件大小： | 1408K |
| 代理商： | MC80C0224K |
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Preliminary
MC80F0208/16/24
MAR. 2005 Ver 0.2
97
The reset should not be activated before V
DD
is restored to its
normal operating level, and must be held active long enough to
allow the oscillator to restart and stabilize.
Note:
After STOP instruction, at least two or more NOP in-
struction should be written.
Ex)
LDM CKCTLR,#0FH ;more than 20ms
LDM SSCR,#5AH
STOP
NOP ;for stabilization time
NOP ;for stabilization time
In the STOP operation, the dissipation of the power associated
with the oscillator and the internal hardware is lowered; however,
the power dissipation associated with the pin interface (depend-
ing on the external circuitry and program) is not directly deter-
mined by the hardware operation of the STOP feature. This point
should be little current flows when the input level is stable at the
power voltage level (V
DD
/V
SS
); however, when the input level
gets higher than the power voltage level (by approximately 0.3 to
0.5V), a current begins to flow. Therefore, if cutting off the out-
put transistor at an I/O port puts the pin signal into the high-im-
pedance state, a current flow across the ports input transistor,
requiring to fix the level by pull-up or other means.
Release the STOP mode
The source for exit from STOP mode is hardware reset, external
interrupt, Timer(EC0,1), Watch Timer, WDT, SIO or UART. Re-
set re-defines all the Control registers but does not change the on-
chip RAM. External interrupts allow both on-chip RAM and
Control registers to retain their values.
If I-flag = 1, the normal interrupt response takes place. If I-flag =
0, the chip will resume execution starting with the instruction fol-
lowing the STOP instruction. It will not vector to interrupt service
routine. (refer to Figure 21-4)
When exit from Stop mode by external interrupt, enough oscilla-
tion stabilization time is required to normal operation. Figure 21-
5 shows the timing diagram. When released from the Stop mode,
the Basic interval timer is activated on wake-up. It is increased
from 00
H
until FF
H
. The count overflow is set to start normal op-
Peripheral
STOP Mode
SLEEP Mode
CPU
Stop
Stop
RAM
Retain
Retain
Basic Interval Timer
Halted
Operates Continuously
Watchdog Timer
Stop (Only operates in RC-WDT mode)
Stop
Watch Timer
Stop
Stop
Timer/Counter
Halted(Only when the event counter mode is
enabled, timer operates normally)
Operates Continuously
Buzzer, ADC
Stop
Stop
SIO
Only operate with external clock
Only operate with external clock
UART
Only operate with external clock
Only operate with external clock
Oscillator
Stop(X
IN
=L, X
OUT
=H)
Oscillation
Sub Oscillator
Oscillation
Oscillation
I/O Ports
Retain
Retain
Control Registers
Retain
Retain
Internal Circuit
Stop mode
Sleep mode
Prescaler
Retain
Active
Address Data Bus
Retain
Retain
Release Source
Reset, Timer(EC0,1), SIO, UART0(using
ACLK0), UART1(using ACLK1)
Watch Timer( RC-WDT mode),
Watchdog Timer( RC-WDT mode),
External Interrupt
Reset, All Interrupts
Table 21-1 Peripheral Operation During Power Saving Mode
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