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參數(shù)資料
| 型號(hào)： | MC80C0208Q |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁(yè)數(shù)： | 99/128頁(yè) |
| 文件大小： | 1408K |
| 代理商： | MC80C0208Q |
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Preliminary
MC80F0208/16/24
MAR. 2005 Ver 0.2
95
21. POWER SAVING OPERATION
The MC80F0208/16/24 has two power-down modes. In power-
down mode, power consumption is reduced considerably. For ap-
plications where power consumption is a critical factor, device
provides two kinds of power saving functions, STOP mode and
SLEEP mode. Table 21-1 shows the status of each Power Saving
Mode. SLEEP mode is entered by the SSCR register to “0Fh”.,
and STOP mode is entered by STOP instruction after the SSCR
register to “5Ah”.
21.1 Sleep Mode
In this mode, the internal oscillation circuits remain active.
Oscillation continues and peripherals are operate normally but
CPU stops. Movement of all peripherals is shown in Table 21-1.
SLEEP mode is entered by setting the SSCR register to “0Fh”. It
is released by Reset or interrupt. To be released by interrupt, in-
terrupt should be enabled before SLEEP mode.
Figure 21-1 STOP and SLEEP Control Register
Release the SLEEP mode
The exit from SLEEP mode is hardware reset or all interrupts.
Reset re-defines all the Control registers but does not change the
on-chip RAM. Interrupts allow both on-chip RAM and Control
registers to retain their values.
If I-flag = 1, the normal interrupt response takes place. If I-flag =
0, the chip will resume execution starting with the instruction fol-
lowing the SLEEP instruction. It will not vector to interrupt serv-
ice routine. (refer to Figure 21-4)
When exit from SLEEP mode by reset, enough oscillation stabi-
lization time is required to normal operation. Figure 21-3 shows
the timing diagram. When released from the SLEEP mode, the
Basic interval timer is activated on wake-up. It is increased from
00
H
until FF
H
. The count overflow is set to start normal opera-
tion. Therefore, before SLEEP instruction, user must be set its
relevant prescaler divide ratio to have long enough time (more
than 20msec). This guarantees that oscillator has started and sta-
bilized. By interrupts, exit from SLEEP mode is shown in Figure
21-2. By reset, exit from SLEEP mode is shown in Figure 21-3.
7
6
5
4
3
2
1
0
INITIAL VALUE: 0000 0000
B
ADDRESS: 0F5
H
SSCR
W
Power Down Control
5A
H
: STOP mode
0F
H
: SLEEP mode
W
W
W
W
W
W
W
NOTE :
To get into STOP mode,
SSCR must be set to 5AH
just before STOP instruction execution.
At STOP mode, Stop & Sleep Control Register (SSCR) value is cleared automatically when released.
To get into SLEEP mode,
SSCR must be set to 0FH
.
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