參數(shù)資料
型號： MC80C0208K
廠商： Electronic Theatre Controls, Inc.
元件分類： 8位微控制器
英文描述： 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 8位單晶片微控制器
文件頁數(shù)： 92/128頁
文件大小： 1408K
代理商： MC80C0208K
MC80F0208/16/24
Preliminary
88
MAR. 2005 Ver 0.2
Figure 19-3 Interrupt Request Flag Register & Interrupt Flag Register
19.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted or the
interrupt latch is cleared to “0” by a reset or an instruction. Inter-
rupt acceptance sequence requires 8 cycles of f
XIN
(2
μ
s at f
X-
IN
=4MHz) after the completion of the current instruction
execution. The interrupt service task is terminated upon execu-
tion of an interrupt return instruction [RETI].
INT3IF
R/W
INT0IF
Timer/Counter 0 interrupt request flag
Serial Communication interrupt request flag
UART1Tx/Rx interrupt request flag
UART0 Tx/Rx interrupt request flag
INITIAL VALUE: 0000 0000
B
ADDRESS: 0EC
H
IRQH
INT1IF
MSB
LSB
SIOIF
T0IF
UART0IF UART1IF
INT2IF
R/W
R/W
External interrupt 3 request flag
External interrupt 2 request flag
External interrupt 1 request flag
External interrupt 0 request flag
R/W
R/W
R/W
R/W
R/W
R/W
T3IF
T1IF
INITIAL VALUE: 0000 0000
B
ADDRESS: 0ED
H
IRQL
T2IF
MSB
R/W
T4IF
Timer/Counter 4 interrupt request flag
Timer/Counter 3 interrupt request flag
Timer/Counter 2 interrupt request flag
Timer/Counter 1 interrupt request flag
R/W
R/W
LSB
R/W
WTIF BITIF
ADCIF WDTIF
R/W
R/W
R/W
Basic Interval Timer interrupt request flag
Watch timer interrupt request flag
Watchdog timer interrupt request flag
A/D Converter interrupt request flag
NOTE1 : In case of using interrupts of Watchdog Timer and Watch Timer together, it is necessary to check IFR in
interrupt service routine to find out which interrupt is occurred, because the Watchdog timer and Watch
timer is shared with interrupt vector address.
These flag bits must be cleared by software after read-
ing this register
.
R/W
-
INITIAL VALUE: --00 0000
B
ADDRESS: 0DF
H
IFR
-
MSB
R/W
UART0 Tx interrupt occurred flag
NOTE3
UART0 Rx interrupt occurred flag
NOTE3
LSB
R/W
R/W
R/W
R/W
RX0IOF TX0IOF
WTIOF
WDT interrupt occurred flag
NOTE1
WT interrupt occurred flag
NOTE1
UART1 Tx interrupt occurred flag
NOTE2
UART1 Rx interrupt occurred flag
NOTE2
RX1IOF TX1IOF
WDTIOF
NOTE2 : In case of using interrupts of UART1 Tx and UART1 Rx together, it is necessary to check IFR in interrupt
service routine to find out which interrupt is occurred, because the UART1 Tx and UART1 Rx is shared
with interrupt vector address.
These flag bits must be cleared by software after reading this register
.
NOTE3 : In case of using interrupts of UART0 Tx and UART0 Rx together, it is necessary to check IFR in interrupt
service routine to find out which interrupt is occurred, because the UART0 Tx and UART0 Rx is shared
with interrupt vector address.
These flag bits must be cleared by software after reading this register
.
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