參數(shù)資料
型號: MC74VHCT573ADT
廠商: ON Semiconductor
文件頁數(shù): 1/7頁
文件大小: 0K
描述: IC LATCH OCTAL D 3ST 20-TSSOP
產(chǎn)品變化通告: Product Obsolescence 24/Jan/2011
標(biāo)準(zhǔn)包裝: 75
系列: 74VHCT
邏輯類型: D 型透明鎖存器
電路: 8:8
輸出類型: 三態(tài)
電源電壓: 4.5 V ~ 5.5 V
獨立電路: 1
延遲時間 - 傳輸: 5.1ns
輸出電流高,低: 8mA,8mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
Semiconductor Components Industries, LLC, 2011
June, 2011 Rev. 5
1
Publication Order Number:
MC74VHCT573A/D
MC74VHCT573A
Octal D-Type Latch
with 3-State Output
The MC74VHCT573A is an advanced high speed CMOS octal latch
with 3state output fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
This 8bit Dtype latch is controlled by a latch enable input and an
output enable input. When the output enable input is high, the eight
outputs are in a high impedance state.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
The VHCT573A input and output (when disabled) structures
provide protection when voltages between 0 V and 5.5 V are applied,
regardless of the supply voltage. These input and output structures
help prevent device destruction caused by supply
voltageinput/output voltage mismatch, battery backup, hot insertion,
etc.
Features
High Speed: tPD = 7.7 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C
TTLCompatible Inputs: VIL = 0.8 V; VIH = 2.0 V
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Designed for 4.5 V to 5.5 V Operating Range
Low Noise: VOLP = 1.6 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
Chip Complexity: 234 FETs or 58.5 Equivalent Gates
These Devices are PbFree and are RoHS Compliant
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAMS
20
1
TSSOP20
SUFFIX DT
CASE 948E
SOIC20WB
SUFFIX DW
CASE 751D
VHCT
573A
ALYWG
G
1
20
1
VHCT573A
AWLYYWWG
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G
= PbFree Package
(Note: Microdot may be in either location)
OE
LE
Q
L
H
L
X
H
L
No Change
Z
INPUTS
OUTPUT
FUNCTION TABLE
D
H
L
X
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