參數(shù)資料
型號: MC74VHC373DWR2
廠商: ON Semiconductor
文件頁數(shù): 2/8頁
文件大?。?/td> 0K
描述: IC LATCH OCTAL D 3ST 20-SOICW
產(chǎn)品變化通告: Product Discontinuation 20/Aug/2008
標準包裝: 1,000
系列: 74VHC
邏輯類型: D 型透明鎖存器
電路: 8:8
輸出類型: 三態(tài)
電源電壓: 2 V ~ 5.5 V
獨立電路: 1
延遲時間 - 傳輸: 4.9ns
輸出電流高,低: 8mA,8mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 20-SOIC
包裝: 帶卷 (TR)
MC74VHC373
http://onsemi.com
2
Figure 1. Logic Diagram
DATA
INPUTS
D0
D1
D2
D3
D4
D5
D6
D7 18
17
14
13
8
7
4
3
1
OE
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
16
15
12
9
6
5
2
NONINVERTING
OUTPUTS
11
LE
OE
LE
Q
L
H
L
X
H
L
No Change
Z
INPUTS
OUTPUT
FUNCTION TABLE
D
H
L
X
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage
– 0.5 to + 7.0
V
Vin
DC Input Voltage
– 0.5 to + 7.0
V
Vout
DC Output Voltage
– 0.5 to VCC + 0.5
V
IIK
Input Diode Current
20
mA
IOK
Output Diode Current
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air,
SOIC Packages
TSSOP Package
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
Derating — SOIC Packages: – 7 mW/
_C from 65_ to 125_C
TSSOP Package: 6.1 mW/
_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage
2.0
5.5
V
Vin
DC Input Voltage
0
5.5
V
Vout
DC Output Voltage
0
VCC
V
TA
Operating Temperature
40
+ 85
_C
tr, tf
Input Rise and Fall Time
VCC = 3.3 V
VCC = 5.0 V
0
100
20
ns/V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
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