參數(shù)資料
型號: MC74VHC1GT125DT1G
廠商: ON SEMICONDUCTOR
元件分類: 總線收發(fā)器
英文描述: AHC/VHC SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO5
封裝: SC-59, SOT-23, TSOP-5
文件頁數(shù): 1/6頁
文件大?。?/td> 89K
代理商: MC74VHC1GT125DT1G
Semiconductor Components Industries, LLC, 2007
February, 2007 Rev. 12
1
Publication Order Number:
MC74VHC1GT125/D
MC74VHC1GT125
Noninverting Buffer /
CMOS Logic Level Shifter
with LSTTLCompatible Inputs
The MC74VHC1GT125 is a single gate noninverting buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The MC74VHC1GT125 requires the 3state control input (OE) to
be set High to place the output into the high impedance state.
The device input is compatible with TTLtype input thresholds and
the output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logiclevel translator from 3 V
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V
CMOS Logic while operating at the highvoltage power supply.
The MC74VHC1GT125 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT125 to be used to interface 5 V circuits to
3 V circuits. The output structures also provide protection when
VCC = 0 V. These input and output structures help prevent device
destruction caused by supply voltage input/output voltage mismatch,
battery backup, hot insertion, etc.
Features
High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
TTLCompatible Inputs: VIL = 0.8 V; VIH = 2 V
CMOSCompatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FETs = 62; Equivalent Gates = 16
PbFree Packages are Available
Figure 1. Pinout (Top View)
IN A
OUT Y
VCC
OE
IN A
OUT Y
GND
OE
Figure 2. Logic Symbol
1
2
3
4
5
PIN ASSIGNMENT
1
2
3
GND
OE
IN A
4
5VCC
OUT Y
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
FUNCTION TABLE
L
H
X
A Input
Y Output
L
H
Z
OE Input
L
H
http://onsemi.com
SC88A/SOT353/SC70
DF SUFFIX
CASE 419A
TSOP5/SOT23/SC59
DT SUFFIX
CASE 483
MARKING
DIAGRAMS
1
5
1
5
1
5
W1 M
G
W1
= Device Code
M
= Date Code*
G
= PbFree Package
1
5
W1 M
G
M
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
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