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參數(shù)資料
| 型號： | MC74VHC1G50DTT3 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 門電路 |
| 英文描述： | AHC/VHC SERIES, 1-INPUT NON-INVERT GATE, PDSO5 |
| 封裝： | SC-59, SOT-23, TSOP-5 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 118K |
| 代理商： | MC74VHC1G50DTT3 |
MC74VHC1G50
http://onsemi.com
5
Figure 6. Carrier Tape Specifications
D1
FOR COMPONENTS
10 PITCHES
CUMULATIVE
TOLERANCE ON
TAPE
±0.2 mm
(
±0.008”)
2.0 mm
× 1.2 mm
AND LARGER
CENTER LINES
OF CAVITY
EMBOSSMENT
USER DIRECTION OF FEED
K0
SEE
NOTE 8.
P0
P2
D
E
F
W
B0
+
K
t
B1
TOP
COVER
TAPE
P
SEE NOTE 8.
A0
FOR MACHINE REFERENCE
ONLY
INCLUDING DRAFT AND RADII
CONCENTRIC AROUND B0
R MIN.
TAPE AND COMPONENTS
SHALL PASS AROUND RADIUS “R”
WITHOUT DAMAGE
BENDING RADIUS
*TOP COVER
TAPE THICKNESS (t1)
0.10 mm
(0.004”) MAX.
EMBOSSED
CARRIER
EMBOSSMENT
TYPICAL
COMPONENT CAVITY
CENTER LINE
TYPICAL
COMPONENT
CENTER LINE
MAXIMUM COMPONENT ROTATION
10
°
CAMBER (TOP VIEW)
ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm
100 mm
(3.937”)
1 mm
(0.039”) MAX
250 mm
(9.843”)
1 mm MAX
TAPE
EMBOSSED CARRIER DIMENSIONS (See Notes 7. and 8.)
Tape
Size
B1
Max
D
D1
E
F
K
P
P0
P2
R
T
W
8 mm
4.35 mm
(0.171”)
1.5 +0.1/
–0.0 mm
(0.059
+0.004/
–0.0”)
1.0 mm
Min
(0.039”)
1.75
±0.1 mm
(0.069
±0.004”)
3.5
±0.5 mm
(1.38
±0.002”)
2.4 mm
(0.094”)
4.0
±0.10 mm
(0.157
±0.004”)
4.0
±0.1 mm
(0.156
±0.004”)
2.0
±0.1 mm
(0.079
±0.002”)
25 mm
(0.98”)
0.3
±0.05 mm
(0.01
+0.0038/
–0.0002”)
8.0
±0.3 mm
(0.315
±0.012”)
7. Metric Dimensions Govern–English are in parentheses for reference only.
8. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0.50 mm max. The component cannot rotate more than 10
° within the determined cavity
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