參數(shù)資料
型號(hào): MC74VHC138D
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: Replaced by TPS40054 : Wide Input Voltage Synchronous Buck Controller 16-HTSSOP -40 to 85
中文描述: AHC/VHC SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16
封裝: PLASTIC, SOIC-16
文件頁(yè)數(shù): 1/7頁(yè)
文件大?。?/td> 164K
代理商: MC74VHC138D
SEMICONDUCTOR TECHNICAL DATA
1
REV 1
Motorola, Inc. 1997
6/97
The MC74VHC138 is an advanced high speed CMOS 3–to–8 decoder
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
When the device is enabled, three Binary Select inputs (A0 – A2)
determine which one of the outputs (Y0 – Y7) will go Low. When enable input
E3 is held Low or either E2 or E1 is held High, decoding function is inhibited
and all outputs go high. E3, E2, and E1 inputs are provided to ease cascade
connection and for use as an address decoder for memory systems.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
High Speed: tPD = 5.7ns (Typ) at VCC = 5V
Low Power Dissipation: ICC = 4
μ
A (Max) at TA = 25
°
C
High Noise Immunity: VNIH = VNIL = 28% VCC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2V to 5.5V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
Chip Complexity: 122 FETs or 30.5 Equivalent Gates
7
Y6
Y7
Y5
Y4
Y3
Y2
Y1
Y0
9
10
11
12
13
14
15
3
2
1
E3
E2
A0
A1
A2
ACTIVE–LOW
OUTPUTS
SELECT
INPUTS
E1
ENABLE
INPUTS
4
5
6
Inputs
E1
Outputs
E3
E2
A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X
X
L
H
H
H
H
H
H
H
H
X
H
X
L
L
L
L
L
L
L
L
H
X
X
L
L
L
L
L
L
L
L
X
X
X
L
L
L
L
H
H
H
H
X
X
X
L
L
H
H
L
L
H
H
X
X
X
L
H
L
H
L
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
FUNCTION TABLE
H = high level (steady state); L = low level (steady state);
X = don’t care
LOGIC DIAGRAM
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
A0
E1
A2
A1
Y7
E3
E2
GND
Y3
Y2
Y1
Y0
VCC
Y5
Y4
Y6
D SUFFIX
16–LEAD SOIC PACKAGE
CASE 751B–05
DT SUFFIX
16–LEAD TSSOP PACKAGE
CASE 948F–01
ORDERING INFORMATION
MC74VHCXXXD
MC74VHCXXXDT
MC74VHCXXXM
SOIC
TSSOP
SOIC EIAJ
M SUFFIX
16–LEAD SOIC EIAJ PACKAGE
CASE 966–01
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