參數(shù)資料
型號(hào): MC74LVX4245DWG
廠商: ON Semiconductor
文件頁(yè)數(shù): 7/10頁(yè)
文件大?。?/td> 0K
描述: IC TXRX OCT TRANSLATING 24-SOIC
標(biāo)準(zhǔn)包裝: 30
系列: 74LVX
邏輯類(lèi)型: 收發(fā)器,非反相
元件數(shù): 1
每個(gè)元件的位元數(shù): 8
輸出電流高,低: 12mA,12mA; 24mA,24mA
電源電壓: 2.7 V ~ 3.6 V,4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SOIC
包裝: 管件
其它名稱(chēng): MC74LVX4245DWG-ND
MC74LVX4245DWGOS
MC74LVX4245
http://onsemi.com
6
Dual Supply Octal Translating Transceiver
The 74LVX4245 is a is a dualsupply device well capable
of bidirectional signal voltage translation. This level shifting
ability provides an excellent interface between low voltage
CPU local bus and a standard 5.0 V I/O bus. The device
control inputs can be controlled by either the low voltage
CPU and core logic or a bus arbitrator with 5.0 V I/O levels.
The LVX4245 is ideal for mixed voltage applications such
as notebook computers using a 3.3 V CPU and 5.0 V
peripheral devices.
Applications:
Mixed Mode Dual Supply Interface Solutions
The LVX4245 is designed to solve 3.0 V / 5.0 V interfaces
when CMOS devices cannot tolerate I/O levels above their
applied VCC. If an I/O pin of a 3.0 V device is driven by a 5.0
V device, the PChannel transistor in the 3.0 V device will
conduct causing current flow from the I/O bus to the 3.0 V
power supply. The result may be destruction of the 3.0 V
device through latchup effects. A current limiting resistor
may be used to prevent destruction, but it causes speed
degradation and needless power dissipation.
A better solution is provided in the LVX4245. It provides
two different output levels that easily handle the dual voltage
interface. The A port is a dedicated 5.0 V port; the B port is
a dedicated 3.0 V port.
Since the LVX4245 is a ‘245 transceiver, the user may
either use it for bidirectional or unidirectional applications.
The center 20 pins are configured to match a ‘245 pinout.
This enables the user to easily replace this level shifter with
a 3.0 V ‘245 device without additional layout work or re
manufacture of the circuit board (when both buses are 3.0 V).
Figure 3. 3.3V/5V Interface Block Diagram
LVX4245
VCCB
VCCA
LVX4245
VCCB
VCCA
EISA - ISA - MCA
(5V I/O LEVELS)
LOW VOLTAGE CPU LOCAL BUS
Powering Up the LVX4245
When powering up the LVX4245, please note that if the
VCCB pin is poweredup well in advance of the VCCA pin,
several milliamps of either ICCA or ICCB current will result.
If the VCCA pin is poweredup in advance of the VCCB pin
then only nanoamps of Icc current will result. In actuality the
VCCB can be powered “slightly” before the VCCA without
the current penalty, but this “setup time” is dependent on the
powerup ramp rate of the VCC pins. With a ramp rate of
approximately 50 mV/ns (50V/
ms) a 25 ns setup time was
observed (VCCB before VCCA). With a 7.0 V/ms rate, the
setup time was about 140ns. When all is said and done, the
safest powerup strategy is to simply power VCCA before
VCCB. One more note: if the VCCB ramp rate is faster than
the VCCA ramp rate then power problems might still occur,
even if the VCCA powerup began prior to the VCCB powerup.
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