參數(shù)資料
型號: MC74LVX4245DW
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: LOW-VOLTAGE CMOS
中文描述: LV/LV-A/LVX/H SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24
封裝: PLASTIC, SOIC-24
文件頁數(shù): 1/9頁
文件大?。?/td> 132K
代理商: MC74LVX4245DW
SEMICONDUCTOR TECHNICAL DATA
1
REV 2
Motorola, Inc. 1997
7/97
"
!
The 74LVX4245 is a 24–pin dual–supply, octal translating transceiver
that is designed to interface between a 5V bus and a 3V bus in a mixed
3V/5V supply environment such as laptop computers using a 3.3V CPU
and 5V LCD display. The A port interfaces with the 5V bus; the B port
interfaces with the 3V bus.
The Transmit/Receive (T/R) input determines the direction of data flow.
Transmit (active–High) enables data from the A port to the B port.
Receive (active–Low) enables data from the B port to the A port. The
Output Enable (OE) input, when High, disables both A and B ports by
placing them in 3–State.
Bi–directional Interface Between 5V and 3V Buses
Control Inputs Compatible with TTL Level
5V Data Flow at A Port and 3V Data Flow at B Port
Outputs Source/Sink 24mA at 5V Bus and 12mA at 3V Bus
Guaranteed Simultaneous Switching Noise Level and Dynamic
Threshold Performance
Available in SOIC and TSSOP Packages
Functionally Compatible with the 74 Series 245
Figure 1. 24–Lead Pinout
(Top View)
23
24
22
21
20
19
18
2
1
3
4
5
6
7
VCCB
17
8
16
9
15
10
VCCBOE
B0
B1
B2
B3
B4
B5
B6
VCCAT/R
A0
A1
A2
A3
A4
A5
A6
A7
14
11
13
12
B7
GND
GND GND
PIN NAMES
Function
Output Enable Input
Transmit/Receive Input
Side A 3–State Inputs or 3–State
Outputs
Side B 3–State Inputs or 3–State
Outputs
Pins
OE
T/R
A0–A7
B0–B7
DW SUFFIX
24–LEAD PLASTIC SOIC PACKAGE
CASE 751E–04
DT SUFFIX
24–LEAD PLASTIC TSSOP PACKAGE
CASE 948H–01
LOW–VOLTAGE CMOS
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