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參數(shù)資料
| 型號： | MC74LVX373DWR2 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 4/7頁 |
| 文件大小： | 0K |
| 描述： | IC LATCH TRANSP OCT 3ST 20-SOICW |
| 產(chǎn)品變化通告： | Product Discontinuation 20/Aug/2008 |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | 74LVX |
| 邏輯類型： | D 型透明鎖存器 |
| 電路： | 8:8 |
| 輸出類型： | 三態(tài) |
| 電源電壓： | 2 V ~ 3.6 V |
| 獨(dú)立電路： | 1 |
| 延遲時(shí)間 - 傳輸： | 5.8ns |
| 輸出電流高，低： | 4mA，4mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC |
| 包裝： | 帶卷 (TR) |
MC74LVX373
http://onsemi.com
4
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
Symbol
Parameter
Test Conditions
TA = 25°C
TA = 40 to 85°C
Unit
Min
Typ
Max
Min
Max
tPLH,
tPHL
Propagation Delay
D to O
VCC = 2.7V
CL = 15pF
CL = 50pF
7.5
10.0
14.5
18.0
1.0
17.5
21.0
ns
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
5.8
8.3
9.3
12.8
1.0
11.0
14.5
tPLH,
tPHL
Propagation Delay
LE to O
VCC = 2.7V
CL = 15pF
CL = 50pF
7.7
10.2
15.0
18.5
1.0
18.5
22.0
ns
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
6.0
8.5
9.7
13.2
1.0
11.5
15.0
tPZL,
tPZH
Output Enable Time
OE to O
VCC = 2.7V
CL = 15pF
RL = 1kW
CL = 50pF
7.7
10.2
15.0
18.5
1.0
18.5
22.0
ns
VCC = 3.3 ± 0.3V
CL = 15pF
RL = 1kW
CL = 50pF
6.0
8.5
9.7
13.2
1.0
11.5
15.0
tPLZ,
tPHZ
Output Disable Time
OE to O
VCC = 2.7V
CL = 50pF
RL = 1kW
9.8
18.0
1.0
21.0
ns
VCC = 3.3 ± 0.3V
CL = 50pF
RL = 1kW
8.2
12.8
1.0
14.5
tOSHL
tOSLH
OutputtoOutput Skew
(Note 1)
VCC = 2.7V
CL = 50pF
VCC = 3.3 ±0.3V
CL = 50pF
1.5
1.5
ns
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGHtoLOW (tOSHL) or LOWtoHIGH (tOSLH); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
TA = 25°C
TA = 40 to 85°C
Unit
Min
Typ
Max
Min
Max
Cin
Input Capacitance
4
10
10
pF
Cout
Maximum ThreeState Output Capacitance
6
pF
CPD
Power Dissipation Capacitance (Note 2)
27
pF
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC/8 (per latch). CPD is used to determine the
noload dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 3.3V, Measured in SOIC Package)
Symbol
Characteristic
TA = 25°C
Unit
Typ
Max
VOLP
Quiet Output Maximum Dynamic VOL
0.5
0.8
V
VOLV
Quiet Output Minimum Dynamic VOL
0.5
0.8
V
VIHD
Minimum High Level Dynamic Input Voltage
2.0
V
VILD
Maximum Low Level Dynamic Input Voltage
0.8
V
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
Symbol
Parameter
Test Conditions
TA = 25°C
TA = 40 to 85°C
Unit
Typ
Limit
tw(h)
Minimum Pulse Width, LE
VCC = 2.7V
VCC = 3.3 ±0.3V
6.5
5.0
7.5
5.0
ns
tsu
Minimum Setup Time, D to LE
VCC = 2.7V
VCC = 3.3 ±0.3V
6.0
4.0
6.0
4.0
ns
th
Minimum Hold Time, D to LE
VCC = 2.7V
VCC = 3.3 ±0.3V
1.0
ns
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