參數(shù)資料
型號: MC74LVX259DT
廠商: ON Semiconductor
文件頁數(shù): 1/10頁
文件大?。?/td> 0K
描述: IC LATCH AADDRESS 8BIT 16-TSSOP
產(chǎn)品變化通告: Product Obsolescence 24/Jan/2011
標(biāo)準(zhǔn)包裝: 96
系列: 74LVX
邏輯類型: D 型,可尋址
電路: 1:8
輸出類型: 標(biāo)準(zhǔn)
電源電壓: 2 V ~ 3.6 V
獨(dú)立電路: 1
延遲時間 - 傳輸: 8ns
輸出電流高,低: 4mA,4mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
Semiconductor Components Industries, LLC, 2011
May, 2011 Rev. 3
1
Publication Order Number:
MC74LVX259/D
MC74LVX259
8-Bit Addressable
Latch/1-of-8 Decoder
CMOS Logic Level Shifter
with LSTTLCompatible Inputs
The MC74LVX259 is an 8bit Addressable Latch fabricated with
silicon gate CMOS technology.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The LVX259 is designed for general purpose storage applications in
digital systems. The device has four modes of operation as shown in
the mode selection table. In the addressable latch mode, the data on
Data In is written into the addressed latch. The addressed latch follows
the data input with all nonaddressed latches remaining in their
previous states. In the memory mode, all latches remain in their
previous state and are unaffected by the Data or Address inputs. In the
oneofeightdecoding or demultiplexing mode, the addressed output
follows the state of Data In with all other outputs in the LOW state. In
the Reset mode, all outputs are LOW and unaffected by the address
and data inputs. When operating the LVX259 as an addressable latch,
changing more than one bit of the address could impose a transient
wrong address. Therefore, this should only be done while in the
memory mode.
The MC74LVX259 input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74LVX259 to be used to interface 5.0 V circuits to 3.0 V
circuits.
Features
High Speed: tPD = 7.0 ns (Typ) at VCC = 3.3 V
Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 28% VCC
CMOSCompatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
These Devices are PbFree and are RoHS Compliant
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAMS
TSSOP16
DT SUFFIX
CASE 948F
SOEIAJ16
M SUFFIX
CASE 966
SOIC16
D SUFFIX
CASE 751B
LVX259G
AWLYWW
LVX259
ALYWG
1
16
1
16
1
16
LVX259 = Specific Device Code
A
= Assembly Location
WL, L
= Wafer Lot
Y
= Year
WW, W = Work Week
G or G = PbFree Package
(Note: Microdot may be in either location)
LVX
259
ALYWG
G
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