AC ELECTRICAL CHARACTERISTICS (Input tr
參數(shù)資料
型號(hào): MC74LVX00MELG
廠商: ON Semiconductor
文件頁(yè)數(shù): 4/7頁(yè)
文件大?。?/td> 0K
描述: IC GATE NAND QUAD 2INP 14-SOEIAJ
標(biāo)準(zhǔn)包裝: 2,000
系列: 74LVX
邏輯類型: 與非門
電路數(shù): 4
輸入數(shù): 2
電源電壓: 2 V ~ 3.6 V
電流 - 靜態(tài)(最大值): 2µA
輸出電流高,低: 4mA,4mA
邏輯電平 - 低: 0.5 V ~ 0.8 V
邏輯電平 - 高: 1.5 V ~ 2.4 V
額定電壓和最大 CL 時(shí)的最大傳播延遲: 9.7ns @ 3V ~ 3.6V,50pF
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: SOEIAJ-14
封裝/外殼: 14-SOIC(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
MC74LVX00
http://onsemi.com
4
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
Symbol
Parameter
Test Conditions
TA = 25°C
TA = 40 to 85°C
Unit
Min
Typ
Max
Min
Max
tPLH,
tPHL
Propagation Delay, Input to
Output
VCC = 2.7 V
CL = 15 pF
CL = 50 pF
5.4
7.9
10.1
13.6
1.0
12.5
16.0
ns
VCC = 3.3 ± 0.3 V CL = 15 pF
CL = 50 pF
4.1
6.6
6.2
9.7
1.0
1.0
7.5
11.0
tOSHL
tOSLH
OutputtoOutput Skew
(Note 1)
VCC = 2.7 V
CL = 50 pF
VCC = 3.3 ±0.3 V
CL = 50 pF
1.5
1.5
ns
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGHtoLOW (tOSHL) or LOWtoHIGH (tOSLH); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
TA = 25°C
TA = 40 to 85°C
Unit
Min
Typ
Max
Min
Max
Cin
Input Capacitance
4
10
10
pF
CPD
Power Dissipation Capacitance (Note 2)
19
pF
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC/4 (per gate). CPD is used to determine the
noload dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 3.3 V, Measured in SOIC Package)
Symbol
Characteristic
TA = 25°C
Unit
Typ
Max
VOLP
Quiet Output Maximum Dynamic VOL
0.3
0.5
V
VOLV
Quiet Output Minimum Dynamic VOL
0.3
0.5
V
VIHD
Minimum High Level Dynamic Input Voltage
2.0
V
VILD
Maximum Low Level Dynamic Input Voltage
0.8
V
Figure 3. Switching Waveforms
VCC
GND
50%
50% VCC
A or B
O
tPHL
tPLH
*Includes all probe and jig capacitance
Figure 4. Test Circuit
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
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