參數(shù)資料
型號(hào): MC74LVQ652DW
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: Power Factor Correction (PFC) and PWM Controller Combo; Package: SOIC; No of Pins: 16; Container: Tape & Reel
中文描述: LVQ SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24
封裝: PLASTIC, SOIC-24
文件頁數(shù): 1/10頁
文件大?。?/td> 244K
代理商: MC74LVQ652DW
SEMICONDUCTOR TECHNICAL DATA
1
REV 0
Motorola, Inc. 1995
12/95
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The MC74LVQ652 is a high performance, non–inverting octal
transceiver/registered transceiver operating from a 2.7 to 3.6V supply.
High impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. The MC74LVQ652 is suitable for memory
address driving and all TTL level bus oriented transceiver applications.
Data on the A or B bus will be clocked into the registers as the
appropriate clock pin goes from a LOW–to–HIGH logic level. Two Output
Enable pins (OEBA, OEAB) are provided to control the transceiver
outputs. In the transceiver mode, data present at the high impedance port
may be stored in either the A or the B register or in both. The select
controls (SBA, SAB) can multiplex stored and real–time (transparent
mode) data. In the isolation mode (both outputs disabled), A data may be
stored in the B register or B data may be stored in the A register. When in
the real–time mode, it is possible to store data without using the internal
registers by simultaneously enabling OEAB and OEBA. In this
configuration, each output reinforces its input.
Designed for 2.7 to 3.6V VCC Operation – Ideal for Low Power/Low
Noise Applications
Guaranteed Simultaneous Switching Noise Level and Dynamic
Threshold Performance
Guaranteed Skew Specifications
Guaranteed Incident Wave Switching into 75
Low Static Supply Current (10
μ
A) Substantially Reduces System Power
Requirements
Latchup Performance Exceeds 500mA
ESD Performance: Human Body Model >2000V
Pinout: 24–Lead Package
(Top View)
23
24
22
21
20
19
18
2
1
3
4
5
6
7
VCC
17
8
16
9
15
10
A6
CBA
SBA OEBA
B0
B1
B2
B3
B4
B5
CAB
SAB OEAB
A0
A1
A2
A3
A4
A5
14
11
A7
13
12
B6
B7
GND
LVQ
DW SUFFIX
PLASTIC SOIC
CASE 751E–04
DT SUFFIX
PLASTIC TSSOP
CASE 948H–01
24
1
24
1
SD SUFFIX
PLASTIC SSOP
CASE 940D–03
24
1
LOW–VOLTAGE CMOS
OCTAL TRANSCEIVER/
REGISTERED TRANSCEIVER
WITH DUAL ENABLE
PIN NAMES
Function
Side A Inputs/Outputs
Side B Inputs/Outputs
Clock Pulse Inputs
Select Control Inputs
Output Enable Inputs
Pins
A0–A7
B0–B7
CAB, CBA
SAB, SBA
OEBA, OEAB
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