參數(shù)資料
型號: MC74HCT74ADR2G
廠商: ON Semiconductor
文件頁數(shù): 1/6頁
文件大?。?/td> 0K
描述: IC FLIP FLOP DUAL SET/RST 14SOIC
標(biāo)準(zhǔn)包裝: 2,500
系列: 74HCT
功能: 設(shè)置(預(yù)設(shè))和復(fù)位
類型: D 型
輸出類型: 差分
元件數(shù): 2
每個元件的位元數(shù): 1
頻率 - 時鐘: 30MHz
延遲時間 - 傳輸: 24ns
觸發(fā)器類型: 正邊沿
輸出電流高,低: 4mA,4mA
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
包裝: 帶卷 (TR)
其它名稱: MC74HCT74ADR2GOS
MC74HCT74ADR2GOS-ND
MC74HCT74ADR2GOSTR
Semiconductor Components Industries, LLC, 2006
October, 2006 Rev. 10
1
Publication Order Number:
MC74HCT74A/D
MC74HCT74A
Dual D FlipFlop with Set
and Reset with LSTTL
Compatible Inputs
HighPerformance SiliconGate CMOS
The MC74HCT74A is identical in pinout to the LS74. This device
may be used as a level converter for interfacing TTL or NMOS outputs
to High Speed CMOS inputs.
This device consists of two D flipflops with individual Set, Reset,
and Clock inputs. Information at a Dinput is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flipflop. The Set
and Reset inputs are asynchronous.
Features
Output Drive Capability: 10 LSTTL Loads
TTL NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 mA
In Compliance With the JEDEC Standard No. 7.0 A Requirements
Chip Complexity: 136 FETs or 34 Equivalent Gates
PbFree Packages are Available
LOGIC DIAGRAM
RESET 1
DATA 1
CLOCK 1
SET 1
RESET 2
DATA 2
CLOCK 2
SET 2
1
2
3
4
13
12
11
10
5
6
9
8
Q1
Q2
PIN 14 = VCC
PIN 7 = GND
Design Criteria
Value
Units
Internal Gate Count
34
ea.
Internal Gate Propagation Delay
1.5
ns
Internal Gate Power Dissipation
5.0
mW
Speed Power Product
.0075
pJ
Equivalent to a twoinput NAND gate.
http://onsemi.com
MARKING
DIAGRAMS
A
= Assembly Location
L, WL
= Wafer Lot
Y, YY
= Year
W, WW = Work Week
G= PbFree Package
SOIC14
D SUFFIX
CASE 751A
14
1
HCT74AG
AWLYWW
1
14
1
PDIP14
N SUFFIX
CASE 646
MC74HCT74AN
AWLYYWWG
1
14
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
PIN ASSIGNMENT
SET 1
CLOCK 1
DATA 1
RESET 1
11
12
13
14
8
9
10
5
4
3
2
1
7
6
SET 2
CLOCK 2
DATA 2
RESET 2
VCC
Q2
GND
Q1
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock Data
Q
LH
X
HL
X
L
H
L
X
H*
HH
H
L
HH
L
H
L
X
No Change
H
X
No Change
H
X
No Change
*Both outputs will remain high as long as Set and
Reset are low, but the output states are unpredict-
able if Set and Reset go high simultaneously.
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