參數(shù)資料
型號(hào): MC74HCT132ADTG
廠商: ON Semiconductor
文件頁數(shù): 1/9頁
文件大?。?/td> 0K
描述: IC GATE NAND QUAD 2NP HS 14TSSOP
標(biāo)準(zhǔn)包裝: 96
系列: 74HCT
邏輯類型: 與非門
電路數(shù): 4
輸入數(shù): 2
特點(diǎn): 施密特觸發(fā)器
電源電壓: 2 V ~ 6 V
電流 - 靜態(tài)(最大值): 1µA
輸出電流高,低: 4mA,4mA
邏輯電平 - 低: 0.5 V ~ 0.6 V
邏輯電平 - 高: 1.9 V ~ 2.1 V
額定電壓和最大 CL 時(shí)的最大傳播延遲: 25ns @ 5V,50pF
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 14-TSSOP
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
包裝: 管件
Semiconductor Components Industries, LLC, 2009
November, 2009 Rev. 1
1
Publication Order Number:
MC74HCT132A/D
MC74HCT132A
Quad 2-Input NAND Gate
with Schmitt-Trigger Inputs
with LSTTL Compatible
Inputs
HighPerformance SiliconGate CMOS
The MC74HCT132A is identical in pinout to the LS132. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
The MC74HCT132A can be used to enhance noise immunity or to
square up slowly changing waveforms.
Features
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements as Defined by JEDEC
Standard No. 7A
Chip Complexity: 72 FETs or 18 Equivalent Gates
These are PbFree Devices
Figure 1. Pin Assignment
11
12
13
14
8
9
10
5
4
3
2
1
7
6
B3
Y4
A4
B4
VCC
Y3
A3
A2
Y1
B1
A1
GND
Y2
B2
MARKING
DIAGRAMS
A
= Assembly Location
L, WL
= Wafer Lot
Y, YY
= Year
W, WW = Work Week
G or G = PbFree Package
PDIP14
N SUFFIX
CASE 646
SOIC14
D SUFFIX
CASE 751A
HCT132AG
AWLYWW
TSSOP14
DT SUFFIX
CASE 948G
HCT
132A
ALYWG
G
1
14
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
Inputs
Output
AB
Y
LL
H
LH
H
HLH
HH
L
FUNCTION TABLE
1
14
http://onsemi.com
MC74HCT132AN
AWLYYWWG
1
14
(Note: Microdot may be in either location)
SOEIAJ14
F SUFFIX
CASE 965
74HCT132A
ALYWG
1
14
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