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參數(shù)資料
| 型號(hào)： | MC74HC948E-02ADT |
| 廠商： | Motorola, Inc. |
| 英文描述： | Octal 3-State Noninverting Transparent Latch |
| 中文描述： | 八路三態(tài)同相透明鎖存器 |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大小： | 246K |
| 代理商： | MC74HC948E-02ADT |
SEMICONDUCTOR TECHNICAL DATA
1
REV 7
Motorola, Inc. 1996
10/96
High–Performance Silicon–Gate CMOS
The MC54/74HC573A is identical in pinout to the LS573. The devices are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes low,
data meeting the setup and hold time becomes latched.
The HC573A is identical in function to the HCT373A but has the data
inputs on the opposite side of the package from the outputs to facilitate PC
board layout.
The HC573A is the noninverting version of the HC563A.
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
μ
A
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 218 FETs or 54.5 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0
D1
D2
D3
D4
D5
D6
D7
LATCH ENABLE
OUTPUT ENABLE
11
1
9
8
7
6
5
4
3
2
19
18
17
16
15
14
13
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PIN 20 = VCC
PIN 10 = GND
NONINVERTING
OUTPUTS
ns
Internal Gate Propagation Delay
1.5
PIN ASSIGNMENT
D4
D2
D1
D0
OUTPUT
ENABLE
GND
D7
D6
D5
D3
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Q3
Q2
Q1
Q0
VCC
LATCH
ENABLE
Q7
Q6
Q5
Q4
FUNCTION TABLE
Inputs
Latch
Enable
Output
Output
Enable
D
Q
L
L
L
H
H
H
L
X
H
L
X
X
H
L
No Change
Z
X = Don’t Care
Z = High Impedance
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
MC74HCXXXADT
Ceramic
Plastic
SOIC
TSSOP
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
1
20
1
20
1
20
DT SUFFIX
TSSOP PACKAGE
CASE 948E–02
1
20
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