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參數(shù)資料
| 型號(hào)： | MC74HC75N |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | Dual 2-Bit Transparent Latch |
| 中文描述： | HC/UH SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 172K |
| 代理商： | MC74HC75N |
SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
High–Performance Silicon–Gate CMOS
The MC74HC75 is identical in pinout to the LS75. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device consists of two independent 2–bit transparent latches. Each
latch stores the input data while Latch Enable is at a logic low. The outputs
follow the data inputs when Latch Enable is at a logic high.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 80 FETs or 20 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0
D1
LATCH
ENABLE
2, 6
3, 7
13, 4
2–BIT
TRANSPARENT
LATCH
16, 10
1, 11
15, 9
14, 8
Q0
Q0
Q1
Q1
PIN 5 = VCC
PIN 12 = GND
FUNCTION TABLE
PIN ASSIGNMENT
Inputs
Outputs
Latch
Enable
D
Q
Q
L
H
X
H
H
L
L
H
Q0
H
L
Q0
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
GND
LEa
Q1a
Q1a
Q0a
Q1b
Q0b
Q0b
LEb
D1a
D0a
Q0a
Q1b
D1b
D0b
VCC
X = don’t care
Q0 = latched data
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ORDERING INFORMATION
MC74HCXXN
MC74HCXXD
Plastic
SOIC
1
16
1
16
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