參數(shù)資料
型號(hào): MC74HC595ADTR2
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs
中文描述: HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16
封裝: LEAD FREE, TSSOP-16
文件頁(yè)數(shù): 2/10頁(yè)
文件大小: 224K
代理商: MC74HC595ADTR2
MC54/74HC595A
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
2
Functional operation should be restricted to the Recommended Operating Conditions.
Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
Ceramic DIP: – 10 mW/ C from 100 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Tstg
TL
Storage Temperature
– 65 to + 150
TSSOP Package
500
450
C
mW
Lead Temperature, 1 mm from Case for 10 Seconds
(Ceramic DIP)
300
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
2.0
0
6.0
V
V
(Figure 1)
+ 125
VCC = 2.0 V
0
400
1000
500
ns
b l
Symbol
Parameter
Test Conditions
di i
V
3.15
4.2
4.2
25 C
2.4 mA
4.5
6.0
4.5
1.35
2.48
5.48
3.15
1.35
3.15
4.2
1.35
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20
μ
A
2.0
1.5
1.5
1.5
V
VIL
Maximum Low–Level Input
Voltage
6.0
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20
μ
A
2.0
5.9
0.5
5.9
5.2
0.5
0.5
V
Minimum High–Level Output
Voltage, QA – QH
Vin = VIH or VIL
20
A
5.9
V
|Iout|
6.0
3.0
5.34
2.34
2.2
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
(Vin or Vout)
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
VCC.
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