參數(shù)資料
型號(hào): MC74HC595ADT
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs
中文描述: HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16
封裝: LEAD FREE, TSSOP-16
文件頁數(shù): 4/10頁
文件大小: 224K
代理商: MC74HC595ADT
MC54/74HC595A
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
4
(CL = 50 pF, Input tr = tf = 6.0 ns)
Unit
Unit
12
10
13
25 C
V
Parameter
Parameter
Symbol
Symbol
18
15
125 C
85 C
15
4.5
6.0
15
tTLH,
M(Figures 1 and 7)
2.0
4.5
75
95
19
110
22
High–Impedance State), QA – QH
CPD
Power Dissipation Capacitance (Per Package)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
300
pF
TIMING REQUIREMENTS
Symbol
b l
Parameter
V
– 55 C
9.0
11
U i
4.5
6.0
15
13
800
400
125 C
19
16
Minimum Setup Time, Serial Data Input A to Shift Clock
6.0
5.0
13
tsu
Minimum Setup Time, Shift Clock to Latch Clock
4.5
5.0
95
22
19
ns
th
Minimum Hold Time, Shift Clock to Serial Data Input A
2.0
10
12
5.0
5.0
5.0
5.0
Minimum Recovery Time, Reset Inactive to Shift Clock
(Figure 2)
4.5
40
9.0
13
15
6.0
Minimum Pulse Width, Reset
(Figure 2)
4.5
9.0
13
15
18
6.0
Minimum Pulse Width, Shift Clock
(Figure 1)
3.0
13
50
11
60
6.0
(Figure 6)
3.0
400
50
11
60
(Figure 1)
3.0
400
800
800
ns
相關(guān)PDF資料
PDF描述
MC74HC595ADTR2 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs
MC74HC595AN 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs
MC74HC595ADT 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with 3-State Outputs
MC74HC595AN 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with 3-State Outputs
MC74HC597AD 8-Bit Serial or Parallel-Input/Serial-Output Shift Register with Input Latch
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