MC74HC540A
http://onsemi.com
5
Figure 3. Switching Waveform
VCC
GND
INPUT A
OUTPUT Y
tPHL
OE1 or OE2
50%
VCC
GND
OUTPUT Y
tPZL
OUTPUT Y
tPZH
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
10%
90%
tPLZ
tPHZ
50%
tPLH
90%
50%
10%
tr
tTHL
tf
tTLH
Figure 4. Switching Waveform
90%
50%
10%
50%
CL*
*Includes all probe and jig capacitance
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 5. Test Circuit
Figure 6. Test Circuit
CL*
*Includes all probe and jig capacitance
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
1kW
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ and tPZH.
Figure 7. Logic Detail
One of Eight
Inverters
INPUT A
OE1
OE2
OUTPUT Y
VCC
To 7 Other Inverters
PIN DESCRIPTIONS
INPUTS
A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8, 9)
Data input pins. Data on these pins appear in inverted form
on the corresponding Y outputs, when the outputs are
enabled.
CONTROLS
OE1, OE2 (PINS 1, 19)
Output enables (activelow). When a low voltage is
applied to both of these pins, the outputs are enabled and the
device functions as an inverter. When a high voltage is
applied to either input, the outputs assume the high
impedance state.
OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
13, 12, 11)
Device outputs. Depending upon the state of the output
enable pins, these outputs are either inverting outputs or
highimpedance outputs.